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[Qemu-devel] [PULL v2 07/28] linux-user: Add infrastructure for handling
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 07/28] linux-user: Add infrastructure for handling MIPS-specific prctl() |
Date: |
Thu, 18 Oct 2018 20:47:32 +0200 |
From: Stefan Markovic <address@hidden>
Add infrastructure for handling MIPS-specific prctl(). This is,
for now, just an empty placeholder. The real handling will be
implemented in subsequent patches.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
linux-user/syscall.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index ae3c0df..d2cc971 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9347,6 +9347,14 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
return ret;
}
#endif
+#ifdef TARGET_MIPS
+ case TARGET_PR_GET_FP_MODE:
+ /* TODO: Implement TARGET_PR_SET_FP_MODE handling.*/
+ return -TARGET_EINVAL;
+ case TARGET_PR_SET_FP_MODE:
+ /* TODO: Implement TARGET_PR_GET_FP_MODE handling.*/
+ return -TARGET_EINVAL;
+#endif /* MIPS */
#ifdef TARGET_AARCH64
case TARGET_PR_SVE_SET_VL:
/*
--
2.7.4
- [Qemu-devel] [PULL v2 04/28] elf: Add Mips_elf_abiflags_v0 structure, (continued)
- [Qemu-devel] [PULL v2 04/28] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 01/28] mailmap: Add an item for Yongbok Kim, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 11/28] target/mips: Add assembler mnemonics list for MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 16/28] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 09/28] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 13/28] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 08/28] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 20/28] target/mips: Add CP0 PWBase register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 15/28] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 17/28] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 07/28] linux-user: Add infrastructure for handling MIPS-specific prctl(),
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 22/28] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 21/28] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 19/28] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 24/28] target/mips: Add reset state for PWSize and PWField registers, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 27/28] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 14/28] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 10/28] target/mips: Add basic description of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 12/28] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/18
- [Qemu-devel] [PULL v2 23/28] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/18