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[Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PW
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers |
Date: |
Wed, 17 Oct 2018 14:33:51 +0200 |
From: Yongbok Kim <address@hidden>
Add reset state for PWSize and PWField registers. The reset state
is different for pre-R6 and R6 (and post-R6) ISAa.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d4d3369..aceda11 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26443,6 +26443,24 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Status |= (1 << CP0St_FR);
}
+ if (env->insn_flags & ISA_MIPS32R6) {
+ /* PTW = 1 */
+ env->CP0_PWSize = 0x40;
+ /* GDI = 12 */
+ /* UDI = 12 */
+ /* MDI = 12 */
+ /* PRI = 12 */
+ /* PTEI = 2 */
+ env->CP0_PWField = 0x0C30C302;
+ } else {
+ /* GDI = 0 */
+ /* UDI = 0 */
+ /* MDI = 0 */
+ /* PRI = 0 */
+ /* PTEI = 2 */
+ env->CP0_PWField = 0x02;
+ }
+
if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) {
/* microMIPS on reset when Config3.ISA is 3 */
env->hflags |= MIPS_HFLAG_M16;
--
2.7.4
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, (continued)
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 16/27] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 02/27] elf: Fix PT_MIPS_XXX constants, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 19/27] target/mips: Add CP0 PWBase register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 24/27] target/mips: Implement hardware page table walker for MIPS32, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 03/27] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/17
- Re: [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1, Peter Maydell, 2018/10/18