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[Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' fl
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size |
Date: |
Wed, 17 Oct 2018 14:33:41 +0200 |
From: Philippe Mathieu-Daudé <address@hidden>
Increase the size of insn_flags holder size to 64 bits. This is
needed for future extensions since existing bits are almost all used.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 2 +-
target/mips/internal.h | 2 +-
target/mips/translate.c | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 37703ea..3b3509c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -811,7 +811,7 @@ struct CPUMIPSState {
int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
- int insn_flags; /* Supported instruction set */
+ uint64_t insn_flags; /* Supported instruction set */
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f..bfe83ee 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -59,7 +59,7 @@ struct mips_def_t {
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
target_ulong CP0_EBaseWG_rw_bitmask;
- int insn_flags;
+ uint64_t insn_flags;
enum mips_mmu_types mmu_type;
};
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4d652dc..ce4a1bd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1987,7 +1987,7 @@ typedef struct DisasContext {
target_ulong saved_pc;
target_ulong page_start;
uint32_t opcode;
- int insn_flags;
+ uint64_t insn_flags;
int32_t CP0_Config1;
int32_t CP0_Config3;
int32_t CP0_Config5;
@@ -2410,7 +2410,7 @@ static inline void check_dspr2(DisasContext *ctx)
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
-static inline void check_insn(DisasContext *ctx, int flags)
+static inline void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@@ -2420,7 +2420,7 @@ static inline void check_insn(DisasContext *ctx, int
flags)
/* This code generates a "reserved instruction" exception if the
CPU has corresponding flag set which indicates that the instruction
has been removed. */
-static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
+static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{
if (unlikely(ctx->insn_flags & flags)) {
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 05/27] linux-user: Add MIPS-specific prctl() options, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 04/27] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 10/27] target/mips: Add assembler mnemonics list for MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 01/27] mailmap: Add an item for Yongbok Kim, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 07/27] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 16/27] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext, Aleksandar Markovic, 2018/10/17