[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 02/21] tcg: access cpu->icount_decr.u16.high with ato
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 02/21] tcg: access cpu->icount_decr.u16.high with atomics |
Date: |
Tue, 16 Oct 2018 10:48:52 -0700 |
From: "Emilio G. Cota" <address@hidden>
Consistently access u16.high with atomics to avoid
undefined behaviour in MTTCG.
Note that icount_decr.u16.low is only used in icount mode,
so regular accesses to it are OK.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
accel/tcg/tcg-all.c | 2 +-
accel/tcg/translate-all.c | 2 +-
qom/cpu.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index 56dbb56a16..3d25bdcc17 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -51,7 +51,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
if (!qemu_cpu_is_self(cpu)) {
qemu_cpu_kick(cpu);
} else {
- cpu->icount_decr.u16.high = -1;
+ atomic_set(&cpu->icount_decr.u16.high, -1);
if (use_icount &&
!cpu->can_do_io
&& (mask & ~old_mask) != 0) {
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index ad5c758246..356dcd0948 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -2341,7 +2341,7 @@ void cpu_interrupt(CPUState *cpu, int mask)
{
g_assert(qemu_mutex_iothread_locked());
cpu->interrupt_request |= mask;
- cpu->icount_decr.u16.high = -1;
+ atomic_set(&cpu->icount_decr.u16.high, -1);
}
/*
diff --git a/qom/cpu.c b/qom/cpu.c
index 92599f3541..20ad54d43f 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -266,7 +266,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->mem_io_pc = 0;
cpu->mem_io_vaddr = 0;
cpu->icount_extra = 0;
- cpu->icount_decr.u32 = 0;
+ atomic_set(&cpu->icount_decr.u32, 0);
cpu->can_do_io = 1;
cpu->exception_index = -1;
cpu->crash_occurred = false;
--
2.17.2
- [Qemu-devel] [PULL 07/21] target/unicore32: remove tlb_flush from uc32_init_fn, (continued)
- [Qemu-devel] [PULL 07/21] target/unicore32: remove tlb_flush from uc32_init_fn, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 14/21] target/arm: Convert to HAVE_CMPXCHG128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 15/21] target/arm: Check HAVE_CMPXCHG128 at translate time, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 12/21] tcg: Split CONFIG_ATOMIC128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 16/21] target/ppc: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 09/21] cputlb: fix assert_cpu_is_self macro, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 13/21] target/i386: Convert to HAVE_CMPXCHG128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 08/21] exec: introduce tlb_init, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 05/21] tcg: distribute tcg_time into TCG contexts, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 06/21] target/alpha: remove tlb_flush from alpha_cpu_initfn, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 02/21] tcg: access cpu->icount_decr.u16.high with atomics,
Richard Henderson <=
- [Qemu-devel] [PULL 17/21] target/s390x: Convert to HAVE_CMPXCHG128 and HAVE_ATOMIC128, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 18/21] target/s390x: Split do_cdsg, do_lpq, do_stpq, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 10/21] cputlb: serialize tlb updates with env->tlb_lock, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 20/21] target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 11/21] tcg: Add tlb_index and tlb_entry helpers, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 19/21] target/s390x: Skip wout, cout helpers if op helper does not return, Richard Henderson, 2018/10/16
- [Qemu-devel] [PULL 21/21] cputlb: read CPUTLBEntry.addr_write atomically, Richard Henderson, 2018/10/16
- Re: [Qemu-devel] [PULL 00/21] tcg patch queue, Peter Maydell, 2018/10/18