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[Qemu-devel] [PATCH v5 09/13] hardfloat: implement float32/64 multiplica
From: |
Emilio G. Cota |
Subject: |
[Qemu-devel] [PATCH v5 09/13] hardfloat: implement float32/64 multiplication |
Date: |
Sat, 13 Oct 2018 19:19:29 -0400 |
Performance results for fp-bench:
1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
mul-single: 126.91 MFlops
mul-double: 118.28 MFlops
- after:
mul-single: 258.02 MFlops
mul-double: 197.96 MFlops
2. ARM Aarch64 A57 @ 2.4GHz
- before:
mul-single: 37.42 MFlops
mul-double: 38.77 MFlops
- after:
mul-single: 73.41 MFlops
mul-double: 76.93 MFlops
3. IBM POWER8E @ 2.1 GHz
- before:
mul-single: 58.40 MFlops
mul-double: 59.33 MFlops
- after:
mul-single: 60.25 MFlops
mul-double: 94.79 MFlops
Signed-off-by: Emilio G. Cota <address@hidden>
---
fpu/softfloat.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 62 insertions(+), 4 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index d5d1c555dc..78837fa9d8 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -1276,8 +1276,8 @@ float16 __attribute__((flatten)) float16_mul(float16 a,
float16 b,
return float16_round_pack_canonical(pr, status);
}
-float32 __attribute__((flatten)) float32_mul(float32 a, float32 b,
- float_status *status)
+static float32 QEMU_SOFTFLOAT_ATTR
+soft_float32_mul(float32 a, float32 b, float_status *status)
{
FloatParts pa = float32_unpack_canonical(a, status);
FloatParts pb = float32_unpack_canonical(b, status);
@@ -1286,8 +1286,8 @@ float32 __attribute__((flatten)) float32_mul(float32 a,
float32 b,
return float32_round_pack_canonical(pr, status);
}
-float64 __attribute__((flatten)) float64_mul(float64 a, float64 b,
- float_status *status)
+static float64 QEMU_SOFTFLOAT_ATTR
+soft_float64_mul(float64 a, float64 b, float_status *status)
{
FloatParts pa = float64_unpack_canonical(a, status);
FloatParts pb = float64_unpack_canonical(b, status);
@@ -1296,6 +1296,64 @@ float64 __attribute__((flatten)) float64_mul(float64 a,
float64 b,
return float64_round_pack_canonical(pr, status);
}
+static float float_mul(float a, float b)
+{
+ return a * b;
+}
+
+static double double_mul(double a, double b)
+{
+ return a * b;
+}
+
+static bool f32_mul_fast(float32 a, float32 b, const struct float_status *s)
+{
+ return float32_is_zero(a) || float32_is_zero(b);
+}
+
+static bool f64_mul_fast(float64 a, float64 b, const struct float_status *s)
+{
+ return float64_is_zero(a) || float64_is_zero(b);
+}
+
+static float32 f32_mul_fast_op(float32 a, float32 b, float_status *s)
+{
+ bool signbit = float32_is_neg(a) ^ float32_is_neg(b);
+
+ return float32_set_sign(float32_zero, signbit);
+}
+
+static float64 f64_mul_fast_op(float64 a, float64 b, float_status *s)
+{
+ bool signbit = float64_is_neg(a) ^ float64_is_neg(b);
+
+ return float64_set_sign(float64_zero, signbit);
+}
+
+float32 __attribute__((flatten))
+float32_mul(float32 a, float32 b, float_status *s)
+{
+ if (QEMU_HARDFLOAT_2F32_USE_FP) {
+ return float_gen2(a, b, s, float_mul, soft_float32_mul, float_is_zon2,
+ NULL, f32_mul_fast, f32_mul_fast_op);
+ } else {
+ return f32_gen2(a, b, s, float_mul, soft_float32_mul, f32_is_zon2,
NULL,
+ f32_mul_fast, f32_mul_fast_op);
+ }
+}
+
+float64 __attribute__((flatten))
+float64_mul(float64 a, float64 b, float_status *s)
+{
+ if (QEMU_HARDFLOAT_2F64_USE_FP) {
+ return double_gen2(a, b, s, double_mul, soft_float64_mul,
+ double_is_zon2, NULL, f64_mul_fast,
f64_mul_fast_op);
+ } else {
+ return f64_gen2(a, b, s, double_mul, soft_float64_mul, f64_is_zon2,
+ NULL, f64_mul_fast, f64_mul_fast_op);
+ }
+}
+
/*
* Returns the result of multiplying the floating-point values `a' and
* `b' then adding 'c', with no intermediate rounding step after the
--
2.17.1
- [Qemu-devel] [PATCH v5 00/13] hardfloat, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 05/13] softfloat: add float{32, 64}_is_zero_or_normal, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 01/13] fp-test: pick TARGET_ARM to get its specialization, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 04/13] softfloat: rename canonicalize to sf_canonicalize, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 03/13] target/tricore: use float32_is_denormal, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 02/13] softfloat: add float{32, 64}_is_{de, }normal, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 10/13] hardfloat: implement float32/64 division, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 09/13] hardfloat: implement float32/64 multiplication,
Emilio G. Cota <=
- [Qemu-devel] [PATCH v5 07/13] fpu: introduce hardfloat, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 06/13] tests/fp: add fp-bench, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 08/13] hardfloat: implement float32/64 addition and subtraction, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 13/13] hardfloat: implement float32/64 comparison, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 11/13] hardfloat: implement float32/64 fused multiply-add, Emilio G. Cota, 2018/10/13
- [Qemu-devel] [PATCH v5 12/13] hardfloat: implement float32/64 square root, Emilio G. Cota, 2018/10/13