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Re: [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of R
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn |
Date: |
Sat, 13 Oct 2018 13:00:18 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> static bool trans_mulw(DisasContext *ctx, arg_mulw *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
> - return true;
> + return trans_arith(ctx, a, &tcg_gen_mul_tl);
> }
> static bool trans_divw(DisasContext *ctx, arg_divw *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
> - return true;
> + return trans_arith_w(ctx, a, &gen_div);
> }
> static bool trans_divuw(DisasContext *ctx, arg_divuw *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
> - return true;
> + return trans_arith_w(ctx, a, &gen_divu);
> }
> static bool trans_remw(DisasContext *ctx, arg_remw *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
> - return true;
> + return trans_arith_w(ctx, a, &gen_rem);
> }
> static bool trans_remuw(DisasContext *ctx, arg_remuw *a, uint32_t insn)
> {
> - gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
> - return true;
> + return trans_arith_w(ctx, a, &gen_remu);
> }
Missing TARGET_RISCV64 checks.
r~
- Re: [Qemu-devel] [PATCH 26/28] target/riscv: Remove gen_system(), (continued)
- [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 24/28] target/riscv: Remove shift and slt insn manual decoding, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 27/28] target/riscv: Remove decode_RV32_64G(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2018/10/12
- Re: [Qemu-devel] [PATCH 25/28] target/riscv: Remove manual decoding of RV32/64M insn,
Richard Henderson <=
- [Qemu-devel] [PATCH 19/28] target/riscv: Replace gen_branch() with trans_branch(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/12