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[Qemu-devel] [PATCH 11/28] target/riscv: Convert RV64F insns to decodetr
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 11/28] target/riscv: Convert RV64F insns to decodetree |
Date: |
Fri, 12 Oct 2018 19:30:30 +0200 |
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvf.inc.c | 70 +++++++++++++++++++++++++
2 files changed, 76 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b6807ef8dd..a629a717dc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -196,3 +196,9 @@ fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV64F Standard Extension (in addition to RV32F) ***
+fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
+fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
+fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c
b/target/riscv/insn_trans/trans_rvf.inc.c
index e24efc76b4..d33a0113c2 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -324,3 +324,73 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_w_x
*a, uint32_t insn)
return true;
}
+
+static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_l_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+
+ return true;
+}
+
+static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt_lu_s *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
+ gen_set_gpr(a->rd, t0);
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+
+ return true;
+}
+
+static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_s_l *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
+
+static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt_s_lu *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
+
+ gen_set_rm(ctx, a->rm);
+ gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
+
+ tcg_temp_free(t0);
+#else
+ gen_exception_illegal(ctx);
+#endif
+ return true;
+}
--
2.19.1
- [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree, (continued)
- [Qemu-devel] [PATCH 07/28] target/riscv: Convert RVXM insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 06/28] target/riscv: Convert RVXI csr insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 05/28] target/riscv: Convert RVXI fence insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 02/28] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 08/28] target/riscv: Convert RV32A insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 11/28] target/riscv: Convert RV64F insns to decodetree,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 10/28] target/riscv: Convert RV32F insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 14/28] target/riscv: Convert RV priv insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 18/28] target/riscv: Remove gen_jalr(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 16/28] target/riscv: Convert quadrant 1 of RVXC insns to decodetree, Bastian Koppelmann, 2018/10/12