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[Qemu-devel] [PATCH 05/20] target/arm: Mark some arrays const
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 05/20] target/arm: Mark some arrays const |
Date: |
Thu, 11 Oct 2018 13:51:51 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 736880ee71..d59ffa1c67 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -72,7 +72,7 @@ static TCGv_i64 cpu_F0d, cpu_F1d;
#include "exec/gen-icount.h"
-static const char *regnames[] =
+static const char * const regnames[] =
{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
@@ -4907,7 +4907,7 @@ static struct {
int nregs;
int interleave;
int spacing;
-} neon_ls_element_type[11] = {
+} const neon_ls_element_type[11] = {
{4, 4, 1},
{4, 4, 2},
{4, 1, 1},
@@ -13089,7 +13089,7 @@ void gen_intermediate_code(CPUState *cpu,
TranslationBlock *tb)
translator_loop(ops, &dc.base, cpu, tb);
}
-static const char *cpu_mode_names[16] = {
+static const char * const cpu_mode_names[16] = {
"usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
"???", "???", "hyp", "und", "???", "???", "???", "sys"
};
--
2.17.1
- [Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vector memory ops, (continued)
- [Qemu-devel] [PATCH 01/20] target/arm: Hoist address increment for vector memory ops, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 02/20] target/arm: Don't call tcg_clear_temp_count, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 09/20] target/arm: Use gvec for NEON_3R_VADD_VSUB insns, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 17/20] target/arm: Use gvec for NEON VLD all lanes, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 11/20] target/arm: Use gvec for NEON_3R_VMUL, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 18/20] target/arm: Reorg NEON VLD/VST all elements, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 05/20] target/arm: Mark some arrays const,
Richard Henderson <=
- [Qemu-devel] [PATCH 03/20] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 13/20] target/arm: Use gvec for VSRA, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 06/20] target/arm: Use gvec for NEON VDUP, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 19/20] target/arm: Promote consecutive memory ops for aa32, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 12/20] target/arm: Use gvec for VSHR, VSHL, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 04/20] target/arm: Promote consecutive memory ops for aa64, Richard Henderson, 2018/10/11
- [Qemu-devel] [PATCH 16/20] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE, Richard Henderson, 2018/10/11