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[Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE |
Date: |
Thu, 11 Oct 2018 13:22:17 +0200 |
From: Stefan Markovic <address@hidden>
Add DSP R3 ASE related bit definition for insn_flags and hflags.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/mips-defs.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index dc0122d..f07b94e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -624,6 +624,7 @@ struct CPUMIPSState {
/* MIPS DSP resources access. */
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
+#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index c8e9979..b27b7ae 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -47,6 +47,7 @@
#define ASE_MDMX 0x00040000
#define ASE_DSP 0x00080000
#define ASE_DSPR2 0x00100000
+#define ASE_DSPR3 0x02000000
#define ASE_MT 0x00200000
#define ASE_SMARTMIPS 0x00400000
#define ASE_MICROMIPS 0x00800000
--
2.7.4
- Re: [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register, (continued)
- [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S>, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 18/22] hw/mips: Update ITU to utilise SAARI/SAAR registers, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 20/22] target/mips: Add DEC feature to mips32r6-generic CPU, Aleksandar Markovic, 2018/10/11
- [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/11