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Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EV
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From: |
Aleksandar Markovic |
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Subject: |
Re: [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions |
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Date: |
Mon, 8 Oct 2018 14:07:50 +0000 |
> From: Dimitrije Nikolic <address@hidden>
>
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
This patch is incomplete. The pool P.LS.E0 has three subpools, and, for each of
them,
corresponding opcodes should be created.
Thanks,
Aleksandar
- [Qemu-devel] [PATCH v2 0/7] Misc MIPS fixes and improvements for October 2018, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 6/7] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 5/7] target/mips: Add availability control for DSP R3 ASE, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 1/7] elf: Fix PT_MIPS_XXX constants, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 7/7] target/mips: Implement emulation of nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 2/7] elf: Add MIPS_ABI_FP_XXX constants, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 3/7] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/05
- [Qemu-devel] [PATCH v2 4/7] target/mips: Add bit definitions for DSP R3 ASE, Aleksandar Markovic, 2018/10/05