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[Qemu-devel] [PULL 30/33] target/arm: Add v8M stack checks for Thumb pus
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/33] target/arm: Add v8M stack checks for Thumb push/pop |
Date: |
Mon, 8 Oct 2018 15:00:01 +0100 |
Add v8M stack checks for the 16-bit Thumb push/pop
encodings: STMDB, STMFD, LDM, LDMIA, LDMFD.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/translate.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 65df8d6975c..ef64d2559de 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12251,7 +12251,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
store_reg(s, rd, tmp);
break;
case 4: case 5: case 0xc: case 0xd:
- /* push/pop */
+ /*
+ * 0b1011_x10x_xxxx_xxxx
+ * - push/pop
+ */
addr = load_reg(s, 13);
if (insn & (1 << 8))
offset = 4;
@@ -12264,6 +12267,17 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
if ((insn & (1 << 11)) == 0) {
tcg_gen_addi_i32(addr, addr, -offset);
}
+
+ if (s->v8m_stackcheck) {
+ /*
+ * Here 'addr' is the lower of "old SP" and "new SP";
+ * if this is a pop that starts below the limit and ends
+ * above it, it is UNKNOWN whether the limit check triggers;
+ * we choose to trigger.
+ */
+ gen_helper_v8m_stackcheck(cpu_env, addr);
+ }
+
for (i = 0; i < 8; i++) {
if (insn & (1 << i)) {
if (insn & (1 << 11)) {
--
2.19.0
- [Qemu-devel] [PULL 22/33] target/arm: Move v7m_using_psp() to internals.h, (continued)
- [Qemu-devel] [PULL 22/33] target/arm: Move v7m_using_psp() to internals.h, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 10/33] target/arm: Clear unused predicate bits for LD1RQ, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 09/33] target/arm: Adjust aarch64_cpu_dump_state for system mode SVE, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 23/33] target/arm: Add v8M stack checks on ADD/SUB/MOV of SP, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 08/33] target/arm: Handle SVE vector length changes in system mode, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 13/33] target/arm: Rewrite helper_sve_st[1234]*_r, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 32/33] target/arm: Add v8M stack checks for MSR to SP_NS, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 33/33] hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 31/33] target/arm: Add v8M stack checks for VLDM/VSTM, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 29/33] target/arm: Add v8M stack checks for T32 load/store single, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 30/33] target/arm: Add v8M stack checks for Thumb push/pop,
Peter Maydell <=
- [Qemu-devel] [PULL 24/33] target/arm: Add some comments in Thumb decode, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 25/33] target/arm: Add v8M stack checks on exception entry, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 28/33] target/arm: Add v8M stack checks for Thumb2 LDM/STM, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 27/33] target/arm: Add v8M stack checks for LDRD/STRD (imm), Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 26/33] target/arm: Add v8M stack limit checks on NS function calls, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 03/33] target/arm: Correct condition for v8M callee stack push, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 06/33] target/arm: Adjust sve_exception_el, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 05/33] target/arm: Define ID_AA64ZFR0_EL1, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 04/33] target/arm: Don't read r4 from v8M exception stackframe twice, Peter Maydell, 2018/10/08
- [Qemu-devel] [PULL 07/33] target/arm: Pass in current_el to fp and sve_exception_el, Peter Maydell, 2018/10/08