Re: [Qemu-devel] [PATCH] fix setting the FPSCR[FR] bit

[Peter Maydell]

On 18 September 2018 at 15:34, Programmingkid <address@hidden> wrote:
> On Sep 17, 2018, at 7:46 PM, Peter Maydell <address@hidden> wrote:
>> See my previous email -- the spec suggests that "round" is
>> "inexact but not overflow".
>
> I couldn't find anything in my pdf document about round being defined as 
> inexact but not overflow. Could you send me a link to your document?

My suggestion was based on the doc at:
https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
which also lets you download the 2.07B spec, which says on page 115:

Floating-Point Fraction Inexact (FI)
 The last Arithmetic or Rounding and Conversion instruction either produced an
 inexact result during rounding or caused a disabled Overflow Exception.

which I took to mean that Inexact is "rounded or overflow", so rounded should be
"inexact but not overflow".

However, reading section 4.6 suggests that it's not quite that simple,
because FR is only set if the fraction part is *incremented*, whereas
Inexact covers also cases where the result is inexact but got rounded
down.

So I now think that we need to implement this flag properly in softfloat,
by having the code that does rounding and sets float_flag_inexact
also set float_flag_round in the correct places. I think also that
float_flag_round is a slightly confusing name for these semantics
when it's in the softfloat code rather than the ppc specific code,
because it isn't set only when the result is rounded, but when the
fractional part is specifically rounded up. Maybe float_flag_frac_inc ?

thanks
-- PMM