qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH 22/35] target/ppc: access cpu->interrupt_request


From: David Gibson
Subject: Re: [Qemu-devel] [PATCH 22/35] target/ppc: access cpu->interrupt_request with atomics
Date: Tue, 18 Sep 2018 14:06:49 +1000
User-agent: Mutt/1.10.1 (2018-07-13)

On Mon, Sep 17, 2018 at 12:30:50PM -0400, Emilio G. Cota wrote:
> From: Paolo Bonzini <address@hidden>
> 
> Cc: David Gibson <address@hidden>
> Cc: Alexander Graf <address@hidden>
> Cc: address@hidden
> Signed-off-by: Paolo Bonzini <address@hidden>
> Signed-off-by: Emilio G. Cota <address@hidden>

Acked-by: David Gibson <address@hidden>

> ---
>  hw/ppc/ppc.c                    |  2 +-
>  target/ppc/excp_helper.c        |  3 ++-
>  target/ppc/kvm.c                |  4 ++--
>  target/ppc/translate_init.inc.c | 17 ++++++++++-------
>  4 files changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index ec4be25f49..ad0cfb2f7c 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -91,7 +91,7 @@ void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
>  
>      LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
>                  "req %08x\n", __func__, env, n_IRQ, level,
> -                env->pending_interrupts, CPU(cpu)->interrupt_request);
> +            env->pending_interrupts, 
> atomic_read(&CPU(cpu)->interrupt_request));
>  
>      if (locked) {
>          qemu_mutex_unlock_iothread();
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 6ffa762033..70ac10e23b 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -753,7 +753,8 @@ static void ppc_hw_interrupt(CPUPPCState *env)
>  
>      qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
>                    __func__, env, env->pending_interrupts,
> -                  cs->interrupt_request, (int)msr_me, (int)msr_ee);
> +                  atomic_read(&cs->interrupt_request),
> +                  (int)msr_me, (int)msr_ee);
>  #endif
>      /* External reset */
>      if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index 9211ee2ee1..8214738c20 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -1336,7 +1336,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
>       * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
>      if (!cap_interrupt_level &&
>          run->ready_for_interrupt_injection &&
> -        (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> +        (atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) &&
>          (env->irq_input_state & (1<<PPC_INPUT_INT)))
>      {
>          /* For now KVM disregards the 'irq' argument. However, in the
> @@ -1378,7 +1378,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu)
>      CPUState *cs = CPU(cpu);
>      CPUPPCState *env = &cpu->env;
>  
> -    if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
> +    if (!(atomic_read(&cs->interrupt_request) & CPU_INTERRUPT_HARD) && 
> msr_ee) {
>          cs->halted = 1;
>          cs->exception_index = EXCP_HLT;
>      }
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index d920d3e538..3ed8298bc7 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -8442,11 +8442,12 @@ static bool ppc_pvr_match_power7(PowerPCCPUClass 
> *pcc, uint32_t pvr)
>  
>  static bool cpu_has_work_POWER7(CPUState *cs)
>  {
> +    uint32_t interrupt_request = atomic_read(&cs->interrupt_request);
>      PowerPCCPU *cpu = POWERPC_CPU(cs);
>      CPUPPCState *env = &cpu->env;
>  
>      if (cs->halted) {
> -        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
> +        if (!(interrupt_request & CPU_INTERRUPT_HARD)) {
>              return false;
>          }
>          if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
> @@ -8470,7 +8471,7 @@ static bool cpu_has_work_POWER7(CPUState *cs)
>          }
>          return false;
>      } else {
> -        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> +        return msr_ee && (interrupt_request & CPU_INTERRUPT_HARD);
>      }
>  }
>  
> @@ -8596,11 +8597,12 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass 
> *pcc, uint32_t pvr)
>  
>  static bool cpu_has_work_POWER8(CPUState *cs)
>  {
> +    uint32_t interrupt_request = atomic_read(&cs->interrupt_request);
>      PowerPCCPU *cpu = POWERPC_CPU(cs);
>      CPUPPCState *env = &cpu->env;
>  
>      if (cs->halted) {
> -        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
> +        if (!(interrupt_request & CPU_INTERRUPT_HARD)) {
>              return false;
>          }
>          if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
> @@ -8632,7 +8634,7 @@ static bool cpu_has_work_POWER8(CPUState *cs)
>          }
>          return false;
>      } else {
> -        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> +        return msr_ee && (interrupt_request & CPU_INTERRUPT_HARD);
>      }
>  }
>  
> @@ -8788,11 +8790,12 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass 
> *pcc, uint32_t pvr)
>  
>  static bool cpu_has_work_POWER9(CPUState *cs)
>  {
> +    uint32_t interrupt_request = atomic_read(&cs->interrupt_request);
>      PowerPCCPU *cpu = POWERPC_CPU(cs);
>      CPUPPCState *env = &cpu->env;
>  
>      if (cs->halted) {
> -        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
> +        if (!(interrupt_request & CPU_INTERRUPT_HARD)) {
>              return false;
>          }
>          /* External Exception */
> @@ -8825,7 +8828,7 @@ static bool cpu_has_work_POWER9(CPUState *cs)
>          }
>          return false;
>      } else {
> -        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> +        return msr_ee && (interrupt_request & CPU_INTERRUPT_HARD);
>      }
>  }
>  
> @@ -10269,7 +10272,7 @@ static bool ppc_cpu_has_work(CPUState *cs)
>      PowerPCCPU *cpu = POWERPC_CPU(cs);
>      CPUPPCState *env = &cpu->env;
>  
> -    return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> +    return msr_ee && (atomic_read(&cs->interrupt_request) & 
> CPU_INTERRUPT_HARD);
>  }
>  
>  /* CPUClass::reset() */

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

Attachment: signature.asc
Description: PGP signature


reply via email to

[Prev in Thread] Current Thread [Next in Thread]