Re: [Qemu-devel] [PATCH 5/8] hw: designware: add read memory region callback

[Paolo Bonzini]

On 12/09/2018 18:01, Li Qiang wrote:
> From: Li Qiang <address@hidden>
> 
> Signed-off-by: Li Qiang <address@hidden>
> ---
>  hw/pci-host/designware.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> index 29ea313798..f5641b5c8c 100644
> --- a/hw/pci-host/designware.c
> +++ b/hw/pci-host/designware.c
> @@ -57,6 +57,12 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root)
>      return DESIGNWARE_PCIE_HOST(bus->parent);
>  }
>  
> +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr,
> +                                              unsigned size)
> +{
> +    return 0;
> +}
> +
>  static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
>                                             uint64_t val, unsigned len)
>  {
> @@ -71,6 +77,7 @@ static void designware_pcie_root_msi_write(void *opaque, 
> hwaddr addr,
>  }
>  
>  static const MemoryRegionOps designware_pci_host_msi_ops = {
> +    .read = designware_pcie_root_msi_read,
>      .write = designware_pcie_root_msi_write,
>      .endianness = DEVICE_LITTLE_ENDIAN,
>      .valid = {
> 

This probably needs to generate an unassigned access too, because the
datasheet says that the device basically traps memory writes.

Generating an unassigned access is probably a good idea for the memory
core; devices can then override the behavior to return zero.  I'm
queuing patches 1-4, with slightly expanded commit messages.

Paolo