Re: [Qemu-devel] [RFC] target/mips: Initial support for MIPS R5900

[Philippe Mathieu-Daudé]

Hi,

On 7/7/18 4:41 PM, Fredrik Noring wrote:
[...]
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -52,6 +52,7 @@
>  #define   ASE_MSA       0x01000000
>  
>  /* Chip specific instructions. */
> +#define              INSN_R5900      0x10000000

We have 4 bits to store the chip-specific instructions and this is the
last bit available.

Any objection to upraise CPUMIPSState.insn_flags to a uint64_t?
I'd then shift the chip-specific bits to the 32 upper bits, to keep this
flag clean.

>  #define              INSN_LOONGSON2E  0x20000000
>  #define              INSN_LOONGSON2F  0x40000000
>  #define              INSN_VR54XX     0x80000000
> @@ -62,6 +63,7 @@
>  #define              CPU_MIPS3       (CPU_MIPS2 | ISA_MIPS3)
>  #define              CPU_MIPS4       (CPU_MIPS3 | ISA_MIPS4)
>  #define              CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
> +#define              CPU_R5900       (CPU_MIPS4 | INSN_R5900)
>  #define              CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
>  #define              CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
[...]

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