[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 11/15] target/xtensa: change SR number checks to ass
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 11/15] target/xtensa: change SR number checks to assertions |
Date: |
Tue, 4 Sep 2018 18:43:48 -0700 |
Opcode decoding with libisa takes care about range of valid group SRs,
like CCOMPARE, IBREAKA, DBREAKA or DBREAKC. Turn range checks in wsr
implementations into assertions.
Signed-off-by: Max Filippov <address@hidden>
---
target/xtensa/translate.c | 65 +++++++++++++++++++++--------------------------
1 file changed, 29 insertions(+), 36 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 93289fd37f1f..0af3f1b16792 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -634,38 +634,34 @@ static bool gen_wsr_atomctl(DisasContext *dc, uint32_t
sr, TCGv_i32 v)
static bool gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
unsigned id = sr - IBREAKA;
+ TCGv_i32 tmp = tcg_const_i32(id);
- if (id < dc->config->nibreak) {
- TCGv_i32 tmp = tcg_const_i32(id);
- gen_helper_wsr_ibreaka(cpu_env, tmp, v);
- tcg_temp_free(tmp);
- gen_jumpi_check_loop_end(dc, 0);
- return true;
- }
- return false;
+ assert(id < dc->config->nibreak);
+ gen_helper_wsr_ibreaka(cpu_env, tmp, v);
+ tcg_temp_free(tmp);
+ gen_jumpi_check_loop_end(dc, 0);
+ return true;
}
static bool gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
unsigned id = sr - DBREAKA;
+ TCGv_i32 tmp = tcg_const_i32(id);
- if (id < dc->config->ndbreak) {
- TCGv_i32 tmp = tcg_const_i32(id);
- gen_helper_wsr_dbreaka(cpu_env, tmp, v);
- tcg_temp_free(tmp);
- }
+ assert(id < dc->config->ndbreak);
+ gen_helper_wsr_dbreaka(cpu_env, tmp, v);
+ tcg_temp_free(tmp);
return false;
}
static bool gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
unsigned id = sr - DBREAKC;
+ TCGv_i32 tmp = tcg_const_i32(id);
- if (id < dc->config->ndbreak) {
- TCGv_i32 tmp = tcg_const_i32(id);
- gen_helper_wsr_dbreakc(cpu_env, tmp, v);
- tcg_temp_free(tmp);
- }
+ assert(id < dc->config->ndbreak);
+ gen_helper_wsr_dbreakc(cpu_env, tmp, v);
+ tcg_temp_free(tmp);
return false;
}
@@ -764,26 +760,23 @@ static bool gen_wsr_icountlevel(DisasContext *dc,
uint32_t sr, TCGv_i32 v)
static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
uint32_t id = sr - CCOMPARE;
- bool ret = false;
-
- if (id < dc->config->nccompare) {
- uint32_t int_bit = 1 << dc->config->timerint[id];
- TCGv_i32 tmp = tcg_const_i32(id);
+ uint32_t int_bit = 1 << dc->config->timerint[id];
+ TCGv_i32 tmp = tcg_const_i32(id);
- tcg_gen_mov_i32(cpu_SR[sr], v);
- tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_start();
- }
- gen_helper_update_ccompare(cpu_env, tmp);
- if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
- gen_io_end();
- gen_jumpi_check_loop_end(dc, 0);
- ret = true;
- }
- tcg_temp_free(tmp);
+ assert(id < dc->config->nccompare);
+ tcg_gen_mov_i32(cpu_SR[sr], v);
+ tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
}
- return ret;
+ gen_helper_update_ccompare(cpu_env, tmp);
+ tcg_temp_free(tmp);
+ if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
+ gen_io_end();
+ gen_jumpi_check_loop_end(dc, 0);
+ return true;
+ }
+ return false;
}
#else
static void gen_check_interrupts(DisasContext *dc)
--
2.11.0
- [Qemu-devel] [PATCH 06/15] target/xtensa: extract test for window underflow exception, (continued)
- [Qemu-devel] [PATCH 06/15] target/xtensa: extract test for window underflow exception, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 07/15] target/xtensa: extract test for alloca exception, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 02/15] target/xtensa: extract test for privileged instruction, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 08/15] target/xtensa: extract test for cpdisabled exception, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 09/15] target/xtensa: extract test for division by zero, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 10/15] target/xtensa: extract unconditional TB termination, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 12/15] target/xtensa: always end TB on CCOUNT access/CCOMPARE write, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 13/15] target/xtensa: extract unconditional TB termination via slot 0, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 15/15] target/xtensa: extract gen_check_interrupts call, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 05/15] target/xtensa: extract test for window overflow exception, Max Filippov, 2018/09/04
- [Qemu-devel] [PATCH 11/15] target/xtensa: change SR number checks to assertions,
Max Filippov <=
- [Qemu-devel] [PATCH 14/15] target/xtensa: make rsr/wsr helpers return void, Max Filippov, 2018/09/04