Re: [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD

[Aleksandar Markovic]

Hi, Craig,

> From: Craig Janeczek <address@hidden>
> Sent: Thursday, August 30, 2018 9:30 PM
> 
> Subject: [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD

> Adds support for emulating the S8LDD MXU instruction.

> Signed-off-by: Craig Janeczek <address@hidden>
> ---
>  v1
>     - initial patch
>  v2
>     - changed bitfield usage to extract32
>     - used deposit_tl instructions instead of shift and bitmask
>  v3
>     - Split gen_mxu function into command specific gen_mxu_<ins> functions
>  v4
>     -Add and use MXU_OPTN3_PTN #defines
>     -Add check for MXUEN

>  target/mips/translate.c | 98 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 98 insertions(+)

> diff --git a/target/mips/translate.c b/target/mips/translate.c

> +    TCGv t0, t1;
> +    TCGLabel *l0;
> +    uint32_t xra, s8, optn3, rb;
> +
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +
> +    l0 = gen_new_label();
> +
> +    xra = extract32(ctx->opcode, 6, 4);
> +    s8 = extract32(ctx->opcode, 10, 8);
> +    optn3 = extract32(ctx->opcode, 18, 3);
> +    rb = extract32(ctx->opcode, 21, 5);
> +
> +    gen_load_mxu_cr(t0);
> +    tcg_gen_andi_tl(t0, t0, MXUEN);
> +    tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0);
> +
> +    gen_load_gpr(t0, rb);
> +    tcg_gen_addi_tl(t0, t0, (int8_t)s8);

I am not sure if this works as desired, with respect to branching. In order to 
survive branching, tcg variables must be initialized with tcg_temp_local_new(), 
rather than with tcg_tem_new(). Please retest, and amend if needed.

Thanks,
Aleksandar