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[Qemu-devel] [PULL v4 19/46] target/mips: Add emulation of misc nanoMIPS
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v4 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf) |
Date: |
Thu, 23 Aug 2018 15:34:09 +0200 |
From: Yongbok Kim <address@hidden>
Add emulation of misc nanoMIPS instructions situated in pool32axf.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 429ad23..c26ea68 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17034,6 +17034,89 @@ static void gen_pool32a0_nanomips_insn(DisasContext
*ctx)
}
}
+static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
+{
+#ifndef CONFIG_USER_ONLY
+ int rt = extract32(ctx->opcode, 21, 5);
+ int rs = extract32(ctx->opcode, 16, 5);
+#endif
+
+ switch (extract32(ctx->opcode, 6, 3)) {
+ case NM_POOL32AXF_4:
+ case NM_POOL32AXF_5:
+ switch (extract32(ctx->opcode, 9, 7)) {
+#ifndef CONFIG_USER_ONLY
+ case NM_TLBP:
+ gen_cp0(env, ctx, OPC_TLBP, 0, 0);
+ break;
+ case NM_TLBR:
+ gen_cp0(env, ctx, OPC_TLBR, 0, 0);
+ break;
+ case NM_TLBWI:
+ gen_cp0(env, ctx, OPC_TLBWI, 0, 0);
+ break;
+ case NM_TLBWR:
+ gen_cp0(env, ctx, OPC_TLBWR, 0, 0);
+ break;
+ case NM_TLBINV:
+ gen_cp0(env, ctx, OPC_TLBINV, 0, 0);
+ break;
+ case NM_TLBINVF:
+ gen_cp0(env, ctx, OPC_TLBINVF, 0, 0);
+ break;
+ case NM_DI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_di(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_EI:
+ check_cp0_enabled(ctx);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_helper_ei(t0, cpu_env);
+ gen_store_gpr(t0, rt);
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ tcg_temp_free(t0);
+ }
+ break;
+ case NM_RDPGPR:
+ gen_load_srsgpr(rs, rt);
+ break;
+ case NM_WRPGPR:
+ gen_store_srsgpr(rs, rt);
+ break;
+ case NM_WAIT:
+ gen_cp0(env, ctx, OPC_WAIT, 0, 0);
+ break;
+ case NM_DERET:
+ gen_cp0(env, ctx, OPC_DERET, 0, 0);
+ break;
+ case NM_ERETX:
+ gen_cp0(env, ctx, OPC_ERET, 0, 0);
+ break;
+#endif
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -17404,6 +17487,14 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
gen_pool32a0_nanomips_insn(ctx);
break;
case NM_POOL32A7:
+ switch (extract32(ctx->opcode, 3, 3)) {
+ case NM_POOL32AXF:
+ gen_pool32axf_nanomips_insn(env, ctx);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
break;
default:
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
- [Qemu-devel] [PULL v4 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, (continued)
- [Qemu-devel] [PULL v4 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 37/46] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 31/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 28/46] target/mips: Implement MT ASE support for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 19/46] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf),
Aleksandar Markovic <=
- [Qemu-devel] [PULL v4 17/46] target/mips: Add emulation of nanoMIPS FP instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 23/46] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 32/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 4, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 35/46] target/mips: Add availability control via bit NMS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 44/46] mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 39/46] elf: Add EM_NANOMIPS value as a valid one for e_machine field, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 36/46] disas: Add support for nanoMIPS platform, Aleksandar Markovic, 2018/08/23