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Re: [Qemu-devel] [PATCH 02/22] hw/misc/mps2-fpgaio: Implement PSCNTR and
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 02/22] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER |
Date: |
Thu, 23 Aug 2018 06:31:45 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 08/20/2018 07:10 AM, Peter Maydell wrote:
> In the MPS2 FPGAIO, PSCNTR is a free-running downcounter with
> a reload value configured via the PRESCALE register, and
> COUNTER counts up by 1 every time PSCNTR reaches zero.
> Implement these counters.
>
> We can just increment the counters migration subsection's
> version ID because we only added it in the previous commit,
> so no released QEMU versions will be using it.
>
> Signed-off-by: Peter Maydell <address@hidden>
> Reviewed-by: Alistair Francis <address@hidden>
> ---
> include/hw/misc/mps2-fpgaio.h | 6 +++
> hw/misc/mps2-fpgaio.c | 97 +++++++++++++++++++++++++++++++++--
> 2 files changed, 99 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- [Qemu-devel] [PATCH 00/22] MPS devices: FPGAIO, timer, watchdogs, MSC, DMA, SPI, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 05/22] hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 02/22] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER, Peter Maydell, 2018/08/20
- Re: [Qemu-devel] [PATCH 02/22] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER,
Richard Henderson <=
- [Qemu-devel] [PATCH 04/22] hw/arm/iotkit: Wire up the dualtimer, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 06/22] hw/arm/iotkit: Wire up the watchdogs, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 01/22] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 07/22] hw/arm/iotkit: Wire up the S32KTIMER, Peter Maydell, 2018/08/20
- [Qemu-devel] [PATCH 03/22] hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module, Peter Maydell, 2018/08/20