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[Qemu-devel] [PULL v2 05/15] target/mips: Fix two instances of shadow va
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 05/15] target/mips: Fix two instances of shadow variables |
Date: |
Thu, 16 Aug 2018 19:48:57 +0200 |
From: Aleksandar Markovic <address@hidden>
Fix two instances of shadow variables. This cleans up entire file
translate.c from shadow variables.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3dd66b6..2b70d1b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -13276,7 +13276,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
gen_arith_imm(ctx, OPC_ADDIU, 29, 29, imm << 2);
} else {
/* JRC16 */
- int rs = extract32(ctx->opcode, 5, 5);
+ rs = extract32(ctx->opcode, 5, 5);
gen_compute_branch(ctx, OPC_JR, 2, rs, 0, 0, 0);
}
break;
@@ -15298,7 +15298,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
} else {
/* ADDIUPC */
int reg = mmreg(ZIMM(ctx->opcode, 23, 3));
- int offset = SIMM(ctx->opcode, 0, 23) << 2;
+ offset = SIMM(ctx->opcode, 0, 23) << 2;
gen_addiupc(ctx, reg, offset, 0, 0);
}
--
2.7.4
- [Qemu-devel] [PULL v2 00/15] MIPS queue for QEMU upstream, August 16, 2018, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 01/15] MAINTAINERS: Update target/mips maintainer's email addresses, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 02/15] target/mips: Avoid case statements formulated by ranges - part 1, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 03/15] target/mips: Avoid case statements formulated by ranges - part 2, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 04/15] target/mips: Mark switch fallthroughs with interpretable comments, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 05/15] target/mips: Fix two instances of shadow variables,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 06/15] target/mips: Update some CP0 registers bit definitions, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 07/15] target/mips: Add CP0 BadInstrX register, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 08/15] target/mips: Implement CP0 Config1.WR bit functionality, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 09/15] target/mips: Don't update BadVAddr register in Debug Mode, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 11/15] elf: Remove duplicate preprocessor constant definition, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 10/15] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 12/15] elf: Add ELF flags for MIPS machine variants, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 14/15] linux-user: Add preprocessor availability control to some syscalls, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 13/15] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Aleksandar Markovic, 2018/08/16
- [Qemu-devel] [PULL v2 15/15] qemu-doc: Amend MIPS-related items, Aleksandar Markovic, 2018/08/16