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[Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe dev
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device |
Date: |
Thu, 16 Aug 2018 09:12:41 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/virt.c | 11 +++++++++++
3 files changed, 13 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak
b/default-configs/riscv32-softmmu.mak
index 35e74bebe9..6e19fdc935 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak
b/default-configs/riscv64-softmmu.mak
index 35e74bebe9..6e19fdc935 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 02652e44ee..28bf35ea56 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,6 +36,7 @@
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "chardev/char.h"
+#include "net/net.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
@@ -445,6 +446,16 @@ static void riscv_virt_board_init(MachineState *machine)
pci_vga_init(pci_bus);
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
--
2.17.1
- [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe, Alistair Francis, 2018/08/16
- [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device,
Alistair Francis <=