Re: [Qemu-devel] [PATCH v9 28/84] target/mips: Add emulation of some common nanoMIPS 32-bit instructions

[Richard Henderson]

On 08/16/2018 07:57 AM, Aleksandar Markovic wrote:
> +            imm = extract32(ctx->opcode, 0, 16);
> +            if (rs != 0) {
> +                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm);
> +                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
> +            } else {
> +                tcg_gen_movi_tl(cpu_gpr[rt], imm);
> +            }

The nanomips pseudocode says ADDIU always sign-extends from 32-bit.

I'm hoping for the sake of nanomips64 that the legacy "inputs to 32-bit
instructions must always be sign-extended" rule has gone?

> +                    } else if (rt == 0 && shift == 5) {
> +                        /* PAUSE */
> +                        if (ctx->hflags & MIPS_HFLAG_BMASK) {
> +                            generate_exception_end(ctx, EXCP_RI);
> +                        }

No delay slots for nanomips, so no BMASK.
Probably best to comment that we're implementing PAUSE as a nop.


r~