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[Qemu-devel] [PATCH] imx_serial: Generate interrupt on receive data read
From: |
Hans-Erik Floryd |
Subject: |
[Qemu-devel] [PATCH] imx_serial: Generate interrupt on receive data ready if enabled |
Date: |
Wed, 15 Aug 2018 15:55:54 +0200 |
Generate an interrupt if USR2_RDR and UCR4_DREN are both set.
Signed-off-by: Hans-Erik Floryd <address@hidden>
---
hw/char/imx_serial.c | 3 ++-
include/hw/char/imx_serial.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 0747db9..1e36319 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -74,8 +74,9 @@ static void imx_update(IMXSerialState *s)
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
/*
* TCEN and TXDC are both bit 3
+ * RDR and DREN are both bit 0
*/
- mask |= s->ucr4 & UCR4_TCEN;
+ mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
usr2 = s->usr2 & mask;
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index ee80da1..c8b7428 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -68,6 +68,7 @@
#define UCR2_RXEN (1<<1) /* Receiver enable */
#define UCR2_SRST (1<<0) /* Reset complete */
+#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
#define UTS1_TXEMPTY (1<<6)
--
2.7.4
- [Qemu-devel] [PATCH] imx_serial: Generate interrupt on receive data ready if enabled,
Hans-Erik Floryd <=