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[Qemu-devel] [PULL 17/45] intc/arm_gic: Add virtual interface register d
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/45] intc/arm_gic: Add virtual interface register definitions |
Date: |
Tue, 14 Aug 2018 19:17:47 +0100 |
From: Luc Michel <address@hidden>
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/gic_internal.h | 65 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index c85427c8e31..1aa888a5762 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -21,6 +21,7 @@
#ifndef QEMU_ARM_GIC_INTERNAL_H
#define QEMU_ARM_GIC_INTERNAL_H
+#include "hw/registerfields.h"
#include "hw/intc/arm_gic.h"
#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
@@ -64,6 +65,70 @@
#define GICC_CTLR_EOIMODE (1U << 9)
#define GICC_CTLR_EOIMODE_NS (1U << 10)
+REG32(GICH_HCR, 0x0)
+ FIELD(GICH_HCR, EN, 0, 1)
+ FIELD(GICH_HCR, UIE, 1, 1)
+ FIELD(GICH_HCR, LRENPIE, 2, 1)
+ FIELD(GICH_HCR, NPIE, 3, 1)
+ FIELD(GICH_HCR, VGRP0EIE, 4, 1)
+ FIELD(GICH_HCR, VGRP0DIE, 5, 1)
+ FIELD(GICH_HCR, VGRP1EIE, 6, 1)
+ FIELD(GICH_HCR, VGRP1DIE, 7, 1)
+ FIELD(GICH_HCR, EOICount, 27, 5)
+
+#define GICH_HCR_MASK \
+ (R_GICH_HCR_EN_MASK | R_GICH_HCR_UIE_MASK | \
+ R_GICH_HCR_LRENPIE_MASK | R_GICH_HCR_NPIE_MASK | \
+ R_GICH_HCR_VGRP0EIE_MASK | R_GICH_HCR_VGRP0DIE_MASK | \
+ R_GICH_HCR_VGRP1EIE_MASK | R_GICH_HCR_VGRP1DIE_MASK | \
+ R_GICH_HCR_EOICount_MASK)
+
+REG32(GICH_VTR, 0x4)
+ FIELD(GICH_VTR, ListRegs, 0, 6)
+ FIELD(GICH_VTR, PREbits, 26, 3)
+ FIELD(GICH_VTR, PRIbits, 29, 3)
+
+REG32(GICH_VMCR, 0x8)
+ FIELD(GICH_VMCR, VMCCtlr, 0, 10)
+ FIELD(GICH_VMCR, VMABP, 18, 3)
+ FIELD(GICH_VMCR, VMBP, 21, 3)
+ FIELD(GICH_VMCR, VMPriMask, 27, 5)
+
+REG32(GICH_MISR, 0x10)
+ FIELD(GICH_MISR, EOI, 0, 1)
+ FIELD(GICH_MISR, U, 1, 1)
+ FIELD(GICH_MISR, LRENP, 2, 1)
+ FIELD(GICH_MISR, NP, 3, 1)
+ FIELD(GICH_MISR, VGrp0E, 4, 1)
+ FIELD(GICH_MISR, VGrp0D, 5, 1)
+ FIELD(GICH_MISR, VGrp1E, 6, 1)
+ FIELD(GICH_MISR, VGrp1D, 7, 1)
+
+REG32(GICH_EISR0, 0x20)
+REG32(GICH_EISR1, 0x24)
+REG32(GICH_ELRSR0, 0x30)
+REG32(GICH_ELRSR1, 0x34)
+REG32(GICH_APR, 0xf0)
+
+REG32(GICH_LR0, 0x100)
+ FIELD(GICH_LR0, VirtualID, 0, 10)
+ FIELD(GICH_LR0, PhysicalID, 10, 10)
+ FIELD(GICH_LR0, CPUID, 10, 3)
+ FIELD(GICH_LR0, EOI, 19, 1)
+ FIELD(GICH_LR0, Priority, 23, 5)
+ FIELD(GICH_LR0, State, 28, 2)
+ FIELD(GICH_LR0, Grp1, 30, 1)
+ FIELD(GICH_LR0, HW, 31, 1)
+
+/* Last LR register */
+REG32(GICH_LR63, 0x1fc)
+
+#define GICH_LR_MASK \
+ (R_GICH_LR0_VirtualID_MASK | R_GICH_LR0_PhysicalID_MASK | \
+ R_GICH_LR0_CPUID_MASK | R_GICH_LR0_EOI_MASK | \
+ R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \
+ R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK)
+
/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
* GICv2 and GICv2 with security extensions:
*/
--
2.18.0
- [Qemu-devel] [PULL 41/45] target/arm: Implement tailchaining for M profile cores, (continued)
- [Qemu-devel] [PULL 41/45] target/arm: Implement tailchaining for M profile cores, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 45/45] target/arm: Fix typo in helper_sve_movz_d, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 20/45] intc/arm_gic: Add virtualization enabled IRQ helper functions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 21/45] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 42/45] target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 27/45] intc/arm_gic: Implement gic_update_virt() function, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 44/45] target/arm: Reorganize SVE WHILE, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 05/45] accel/tcg: Pass read access type through to io_readx(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 02/45] nvic: Handle ARMv6-M SCS reserved registers, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 09/45] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code(), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 17/45] intc/arm_gic: Add virtual interface register definitions,
Peter Maydell <=
- [Qemu-devel] [PULL 18/45] intc/arm_gic: Add virtualization extensions helper macros and functions, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 23/45] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq), Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 25/45] intc/arm_gic: Wire the vCPU interface, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 26/45] intc/arm_gic: Implement the virtual interface registers, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 30/45] xlnx-zynqmp: Improve GIC wiring and MMIO mapping, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 29/45] intc/arm_gic: Improve traces, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 33/45] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 37/45] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 40/45] target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining, Peter Maydell, 2018/08/14
- [Qemu-devel] [PULL 43/45] target/arm: Fix typo in do_sat_addsub_64, Peter Maydell, 2018/08/14