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[Qemu-devel] [PATCH 13/29] vmsvga: Add support for extended FIFO registe
From: |
Liran Alon |
Subject: |
[Qemu-devel] [PATCH 13/29] vmsvga: Add support for extended FIFO registers |
Date: |
Thu, 9 Aug 2018 14:46:26 +0300 |
Supporting extended FIFO registers is required to support
SVGA_FIFO_FENCE which allows guest to receive interrupt when FIFO is
processed up to a specified fence.
Thus, as a preperation for supporting SVGA_FIFO_FENCE, add extened
FIFO registers support. Note that exposing SVGA_CAP_EXTENDED_FIFO
requires to support the following registers: SVGA_FIFO_CAPABILITIES,
SVGA_FIFO_FLAGS and SVGA_FIFO_3D_HWVERSION.
For more information on how SVGA_FIFO_3D_HWVERSION is negoitated, see
SVGA3D_Init() in VMware SVGA development kit.
Reviewed-by: Darren Kenny <address@hidden>
Signed-off-by: Liran Alon <address@hidden>
---
hw/display/vmware_vga.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c
index 8eeb0efc9cab..91f990544e14 100644
--- a/hw/display/vmware_vga.c
+++ b/hw/display/vmware_vga.c
@@ -1033,6 +1033,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t
address)
SVGA_CAP_CURSOR_BYPASS;
}
#endif
+ caps |= SVGA_CAP_EXTENDED_FIFO;
ret = caps;
break;
@@ -1138,6 +1139,8 @@ static void vmsvga_value_write(void *opaque, uint32_t
address, uint32_t value)
} else {
vga_dirty_log_start(&s->vga);
}
+ if (s->enable)
+ s->fifo[SVGA_FIFO_3D_HWVERSION] = 0; /* 3D disabled */
break;
case SVGA_REG_WIDTH:
@@ -1384,6 +1387,8 @@ static void vmsvga_init(DeviceState *dev, struct
vmsvga_state_s *s,
&error_fatal);
s->fifo = (uint32_t *)memory_region_get_ram_ptr(&s->fifo_ram);
s->num_fifo_regs = SVGA_FIFO_NUM_REGS;
+ s->fifo[SVGA_FIFO_CAPABILITIES] = 0;
+ s->fifo[SVGA_FIFO_FLAGS] = 0;
vga_common_init(&s->vga, OBJECT(dev));
vga_init(&s->vga, OBJECT(dev), address_space, io, true);
--
1.9.1
- [Qemu-devel] [PATCH 05/29] vmsvga: Show registers and commands on debug output as decimals, (continued)
- [Qemu-devel] [PATCH 05/29] vmsvga: Show registers and commands on debug output as decimals, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 06/29] vmsvga: Fix parse of SVGA_CMD_UPDATE_VERBOSE to consider additional opaque cookie, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 07/29] vmsvga: Handle SVGA_CMD_FRONT_ROP_FILL command, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 08/29] vmsvga: Parse SVGA_CMD_FENCE command to avoid FIFO desync, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 09/29] vmsvga: Account for length of command word when parsing commands, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 10/29] vmsvga: Remove treatment of deprecated commands as Nop, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 11/29] vmsvga: Remove handler of SVGA_CMD_INVALID_CMD, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 12/29] vmsvga: Add definitions of FIFO registers and report their number, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 13/29] vmsvga: Add support for extended FIFO registers,
Liran Alon <=
- [Qemu-devel] [PATCH 14/29] vmsvga: Setup interrupt pin, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 15/29] vmsvga: Add interrupt mask and status registers, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 16/29] vmsvga: Add framework code for SVGA command to raise interrupt, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 17/29] vmsvga: Define interrupt source flags for interrupt status and mask registers, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 18/29] vmsvga: Add support for SVGA_IRQFLAG_FIFO_PROGRESS, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 19/29] vmsvga: Handle SVGA_CMD_FENCE command, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 20/29] vmsvga: Use standard names for params defining hardware cursor image, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 21/29] vmsvga: Use AND mask bpp parameter in SVGA_CMD_DEFINE_CURSOR, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 22/29] vmsvga: Increase size of cursor AND bitmask, Liran Alon, 2018/08/09
- [Qemu-devel] [PATCH 23/29] vmsvga: Implement initial support for rgb-alpha cursors, Liran Alon, 2018/08/09