Re: [Qemu-devel] [kvm-unit-tests PATCH v2 3/4] arm/arm64: GICv2: add GICD_IPRIORITYR testing

[Andrew Jones]

On Fri, Jul 20, 2018 at 04:39:41PM +0100, Andre Przywara wrote:
> Some tests for the IPRIORITY registers. The significant number of bits
> is IMPLEMENTATION DEFINED, but should be the same for every IRQ.
> Also these registers must be byte-accessible.
> Check that accesses beyond the implemented IRQ limit are actually
> read-as-zero/write-ignore.
> 
> Signed-off-by: Andre Przywara <address@hidden>
> ---
>  arm/gic.c | 79 
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 79 insertions(+)
> 
> diff --git a/arm/gic.c b/arm/gic.c
> index 23cb9a4..57a2995 100644
> --- a/arm/gic.c
> +++ b/arm/gic.c
> @@ -354,6 +354,83 @@ static void test_typer_v2(uint32_t reg)
>              nr_gic_cpus);
>  }
>  
> +#define BYTE(reg32, byte) (((reg32) >> ((byte) * 8)) & 0xff)
> +#define REPLACE_BYTE(reg32, byte, new) (((reg32) & ~(0xff << ((byte) * 8))) 
> |\
> +                                     ((new) << ((byte) * 8)))
> +
> +/*
> + * Some registers are byte accessible, do a byte-wide read and write of known
> + * content to check for this.
> + * Apply a @mask to cater for special register properties.
> + * @pattern contains the value already in the register.
> + */
> +static void test_byte_access(void *base_addr, u32 pattern, u32 mask)
> +{
> +     u32 reg = readb(base_addr + 1);
> +
> +     report("byte reads successful (0x%08x => 0x%02x)",
> +            reg == (BYTE(pattern, 1) & (mask >> 8)),
> +            pattern & mask, reg);
> +
> +     pattern = REPLACE_BYTE(pattern, 2, 0x1f);
> +     writeb(BYTE(pattern, 2), base_addr + 2);
> +     reg = readl(base_addr);
> +     report("byte writes successful (0x%02x => 0x%08x)",
> +            reg == (pattern & mask), BYTE(pattern, 2), reg);
> +}

Hmm, should the above test prepare itself for a potential alignment fault?

Thanks,
drew