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[Qemu-devel] [PATCH v6 56/77] mips_malta: Setup GT64120 BARs in nanoMIPS
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 56/77] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader |
Date: |
Thu, 2 Aug 2018 16:16:43 +0200 |
From: Paul Burton <address@hidden>
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that
they are setup in the MIPS32 bootloader. This is necessary for Linux to
be able to access peripherals, including the UART.
Signed-off-by: Paul Burton <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
---
hw/mips/mips_malta.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4bc9036..d1a7c1f 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -664,6 +664,79 @@ static void write_bootloader_nanomips(uint8_t *base,
int64_t run_addr,
/* lui a3,%hi(loaderparams.ram_low_size) */
stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
/* ori a3,a3,%lo(loaderparams.ram_low_size) */
+
+ /* Load BAR registers as done by YAMON */
+ stw_p(p++, 0xe040); stw_p(p++, 0x0681);
+ /* lui t1, %hi(0xb4000000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
+ /* lui t0, %hi(0xdf000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00df);
+ /* addiu[32] t0, $0, 0xdf */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9068);
+ /* sw t0, 0x68(t1) */
+
+ stw_p(p++, 0xe040); stw_p(p++, 0x077d);
+ /* lui t1, %hi(0xbbe00000) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0801);
+ /* lui t0, %hi(0xc0000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
+ /* addiu[32] t0, $0, 0xc0 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9048);
+ /* sw t0, 0x48(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0800);
+ /* lui t0, %hi(0x40000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x0040);
+ /* addiu[32] t0, $0, 0x40 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9050);
+ /* sw t0, 0x50(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0001);
+ /* lui t0, %hi(0x80000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x0080);
+ /* addiu[32] t0, $0, 0x80 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9058);
+ /* sw t0, 0x58(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
+ /* lui t0, %hi(0x3f000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x003f);
+ /* addiu[32] t0, $0, 0x3f */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9060);
+ /* sw t0, 0x60(t1) */
+
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0821);
+ /* lui t0, %hi(0xc1000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
+ /* addiu[32] t0, $0, 0xc1 */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9080);
+ /* sw t0, 0x80(t1) */
+#ifdef TARGET_WORDS_BIGENDIAN
+ stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
+ /* lui t0, %hi(0x5e000000) */
+#else
+ stw_p(p++, 0x0020); stw_p(p++, 0x005e);
+ /* addiu[32] t0, $0, 0x5e */
+#endif
+ stw_p(p++, 0x8422); stw_p(p++, 0x9088);
+ /* sw t0, 0x88(t1) */
+
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
stw_p(p++, NM_HI2(kernel_entry));
/* lui t9,%hi(kernel_entry) */
--
1.9.1
- [Qemu-devel] [PATCH v6 46/77] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, (continued)
- [Qemu-devel] [PATCH v6 46/77] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 47/77] target/mips: Implement CP0 Config1.WR bit functionality, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 48/77] target/mips: Adjust exception_resume_pc() for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 49/77] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 50/77] target/mips: Adjust set_pc() for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 51/77] target/mips: Fix ERET/ERETNC behavior related to ADEL exception, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 52/77] elf: Add nanoMIPS specific variations in ELF header fields, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 53/77] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 54/77] elf: Don't check FCR31_NAN2008 bit for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 55/77] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 56/77] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 57/77] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 58/77] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 59/77] gdbstub: Add XML support for GDB for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 60/77] target/mips: Add definition of nanoMIPS I7200 CPU, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 61/77] linux-user: Add syscall numbers for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 62/77] linux-user: Add target_signal.h header for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 63/77] linux-user: Add termbits.h header for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 64/77] linux-user: Update syscall_defs.h header for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 65/77] linux-user: Add target_fcntl.h header for nanoMIPS, Stefan Markovic, 2018/08/02