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[Qemu-devel] [PATCH v6 19/77] target/mips: Add emulation of nanoMIPS 16-
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 19/77] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions |
Date: |
Thu, 2 Aug 2018 16:16:06 +0200 |
From: Yongbok Kim <address@hidden>
Add emulation of nanoMIPS 16-bit arithmetic instructions.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index aba42be..d6f8dfc 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16522,6 +16522,131 @@ static inline int decode_gpr_gpr4_zero(int r)
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
+ uint32_t op;
+ int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
+ int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+ int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+ int imm;
+
+ /* make sure instructions are on a halfword boundary */
+ if (ctx->base.pc_next & 0x1) {
+ TCGv tmp = tcg_const_tl(ctx->base.pc_next);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+ tcg_temp_free(tmp);
+ generate_exception_end(ctx, EXCP_AdEL);
+ return 2;
+ }
+
+ op = extract32(ctx->opcode, 10, 6);
+ switch (op) {
+ case NM_P16_MV:
+ break;
+ case NM_P16_SHIFT:
+ break;
+ case NM_P16C:
+ break;
+ case NM_P16_A1:
+ switch (extract32(ctx->opcode, 6, 1)) {
+ case NM_ADDIUR1SP:
+ imm = extract32(ctx->opcode, 0, 6) << 2;
+ gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P16_A2:
+ switch (extract32(ctx->opcode, 3, 1)) {
+ case NM_ADDIUR2:
+ imm = extract32(ctx->opcode, 0, 3) << 2;
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rs, imm);
+ break;
+ case NM_P_ADDIURS5:
+ rt = extract32(ctx->opcode, 5, 5);
+ if (rt != 0) {
+ /* imm = sign_extend(s[3] . s[2:0] , from_nbits = 4) */
+ imm = (sextract32(ctx->opcode, 4, 1) << 3) |
+ (extract32(ctx->opcode, 0, 3));
+ gen_arith_imm(ctx, OPC_ADDIU, rt, rt, imm);
+ }
+ break;
+ }
+ break;
+ case NM_P16_ADDU:
+ switch (ctx->opcode & 0x1) {
+ case NM_ADDU16:
+ gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+ break;
+ case NM_SUBU16:
+ gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+ break;
+ }
+ break;
+ case NM_P16_4X4:
+ rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+ rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+ rt = decode_gpr_gpr4(rt);
+ rs = decode_gpr_gpr4(rs);
+ switch ((extract32(ctx->opcode, 7, 2) & 0x2) |
+ (extract32(ctx->opcode, 3, 1))) {
+ case NM_ADDU4X4:
+ gen_arith(ctx, OPC_ADDU, rt, rs, rt);
+ break;
+ case NM_MUL4X4:
+ gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
+ break;
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_LI16:
+ break;
+ case NM_ANDI16:
+ break;
+ case NM_P16_LB:
+ break;
+ case NM_P16_LH:
+ break;
+ case NM_LW16:
+ break;
+ case NM_LWSP16:
+ break;
+ case NM_LW4X4:
+ break;
+ case NM_SW4X4:
+ break;
+ case NM_LWGP16:
+ break;
+ case NM_SWSP16:
+ break;
+ case NM_SW16:
+ break;
+ case NM_SWGP16:
+ break;
+ case NM_BC16:
+ break;
+ case NM_BALC16:
+ break;
+ case NM_BEQZC16:
+ break;
+ case NM_BNEZC16:
+ break;
+ case NM_P16_BR:
+ break;
+ case NM_P16_SR:
+ break;
+ case NM_MOVEP:
+ break;
+ case NM_MOVEPREV:
+ break;
+ default:
+ break;
+ }
+
return 2;
}
--
1.9.1
- [Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, (continued)
- [Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 10/77] elf: Remove duplicate preprocessor constant definition, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 11/77] elf: Add ELF flags for MIPS machine variants, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 12/77] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 13/77] linux-user: Add preprocessor availability control to some syscalls, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 14/77] target/mips: Add preprocessor constants for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 15/77] target/mips: Add nanoMIPS base instruction set opcodes, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 16/77] target/mips: Add nanoMIPS DSP ASE opcodes, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 17/77] target/mips: Add placeholder and invocation of decode_nanomips_opc(), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 18/77] target/mips: Add nanoMIPS decoding and extraction utilities, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 19/77] target/mips: Add emulation of nanoMIPS 16-bit arithmetic instructions,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 20/77] target/mips: Add emulation of nanoMIPS 16-bit branch instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 21/77] target/mips: Add emulation of nanoMIPS 16-bit shift instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 22/77] target/mips: Add emulation of nanoMIPS 16-bit misc instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 23/77] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 24/77] target/mips: Add emulation of nanoMIPS 16-bit logic instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 25/77] target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 26/77] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Stefan Markovic, 2018/08/02