[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v6 06/77] target/mips: Add CP0 BadInstrX register
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v6 06/77] target/mips: Add CP0 BadInstrX register |
Date: |
Thu, 2 Aug 2018 16:15:53 +0200 |
From: Stefan Markovic <address@hidden>
Add CP0 BadInstrX register. This register will be used in nanoMIPS.
Reviewed-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
target/mips/translate.c | 22 +++++++++++++++++++++-
3 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 77c638c..009202c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -323,6 +323,7 @@ struct CPUMIPSState {
target_ulong CP0_BadVAddr;
uint32_t CP0_BadInstr;
uint32_t CP0_BadInstrP;
+ uint32_t CP0_BadInstrX;
int32_t CP0_Count;
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 20100d5..5ba78ac 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 10,
- .minimum_version_id = 10,
+ .version_id = 11,
+ .minimum_version_id = 11,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d6eccc9..432d1a6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5315,7 +5315,13 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
- default:
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+ tcg_gen_andi_tl(arg, arg, ~0xffff);
+ rn = "BadInstrX";
+ break;
+ default:
goto cp0_unimplemented;
}
break;
@@ -6006,6 +6012,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6711,6 +6721,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
rn = "BadInstrP";
break;
+ case 3:
+ CP0_CHECK(ctx->bi);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+ tcg_gen_andi_tl(arg, arg, ~0xffff);
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7385,6 +7401,10 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
/* ignored */
rn = "BadInstrP";
break;
+ case 3:
+ /* ignored */
+ rn = "BadInstrX";
+ break;
default:
goto cp0_unimplemented;
}
--
1.9.1
- [Qemu-devel] [PATCH v6 00/77] Add nanoMIPS support to QEMU, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 01/77] MAINTAINERS: Update target/mips maintainer's email addresses, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 02/77] target/mips: Avoid case statements formulated by ranges, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 03/77] target/mips: Mark switch fallthroughs with interpretable comments, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 04/77] target/mips: Fix two instances of shadow variables, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 05/77] target/mips: Update some CP0 registers bit definitions, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 06/77] target/mips: Add CP0 BadInstrX register,
Stefan Markovic <=
- [Qemu-devel] [PATCH v6 07/77] target/mips: Add gen_op_addr_addi(), Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 08/77] target/mips: Don't update BadVAddr register in Debug Mode, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 09/77] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 10/77] elf: Remove duplicate preprocessor constant definition, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 11/77] elf: Add ELF flags for MIPS machine variants, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 12/77] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 13/77] linux-user: Add preprocessor availability control to some syscalls, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 14/77] target/mips: Add preprocessor constants for nanoMIPS, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 15/77] target/mips: Add nanoMIPS base instruction set opcodes, Stefan Markovic, 2018/08/02
- [Qemu-devel] [PATCH v6 16/77] target/mips: Add nanoMIPS DSP ASE opcodes, Stefan Markovic, 2018/08/02