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[Qemu-devel] [Bug 1777777] Re: arm9 clock pending (SP804)
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [Bug 1777777] Re: arm9 clock pending (SP804) |
Date: |
Mon, 30 Jul 2018 18:38:48 -0000 |
Sorry, I should have been clearer. Please can you provide a test case
binary and QEMU command line that reproduces the problem (including what
the expected output is and what the actual output is)?
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https://bugs.launchpad.net/bugs/1777777
Title:
arm9 clock pending (SP804)
Status in QEMU:
New
Bug description:
Hello all,
I'm using the versatilepb board and the timer Interrupt Mask Status
register (offset 0x14 of the SP804) does not seem to be working
properly on the latest qemu-2.12. I tried on the 2.5 (i believe this
is the mainstream version that comes with Linux) and it works
perfectly.
What happens is that the pending bit does not seem to be set in some
scenarios. In my case, I see the timer value decreasing to 0 and then
being reset to the reload value and neither does the interrupt is
triggered nor the pending bit is set.
I believe this is a matter of timing since in the "long" run the
system eventually catches up (after a few microseconds).
Thank you
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