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Re: [Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters |
Date: |
Mon, 30 Jul 2018 11:45:54 +0100 |
On 25 May 2018 at 14:17, Richard Henderson <address@hidden> wrote:
> On 05/24/2018 11:24 PM, Michael Clark wrote:
>> This patch enables mhpmcounter3h through mhpmcounter31h on RV32.
>> Previously the RV32 h versions (high 32-bits of 64-bit counters)
>> of these counters would trap with an illegal instruction instead
>> of returning 0 as intended.
>>
>> Reported-by: Richard Henderson <address@hidden>
>> Signed-off-by: Michael Clark <address@hidden>
>> ---
>> target/riscv/op_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Fixes: Coverity CID 1390849
> Reviewed-by: Richard Henderson <address@hidden>
Ping -- Coverity is still complaining about this -- did this
patch get lost?
thanks
-- PMM
- Re: [Qemu-devel] [PATCH] RISC-V: Correct typo in RV32 perf counters,
Peter Maydell <=