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[Qemu-devel] [PATCH v5 03/20] intc/arm_gic: Remove some dead code and pu
From: |
Luc Michel |
Subject: |
[Qemu-devel] [PATCH v5 03/20] intc/arm_gic: Remove some dead code and put some functions static |
Date: |
Fri, 27 Jul 2018 11:54:04 +0200 |
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 23 ++---------------------
hw/intc/gic_internal.h | 4 ----
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 53b749d216..b8eba6e594 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -69,11 +69,11 @@ static inline bool gic_has_groups(GICState *s)
return s->revision == 2 || s->security_extn;
}
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
-void gic_update(GICState *s)
+static void gic_update(GICState *s)
{
int best_irq;
int best_prio;
int irq;
int irq_level, fiq_level;
@@ -135,23 +135,10 @@ void gic_update(GICState *s)
qemu_set_irq(s->parent_irq[cpu], irq_level);
qemu_set_irq(s->parent_fiq[cpu], fiq_level);
}
}
-void gic_set_pending_private(GICState *s, int cpu, int irq)
-{
- int cm = 1 << cpu;
-
- if (gic_test_pending(s, irq, cm)) {
- return;
- }
-
- DPRINTF("Set %d pending cpu %d\n", irq, cpu);
- GIC_DIST_SET_PENDING(irq, cm);
- gic_update(s);
-}
-
static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target)
{
if (level) {
GIC_DIST_SET_LEVEL(irq, cm);
@@ -577,11 +564,11 @@ static void gic_deactivate_irq(GICState *s, int cpu, int
irq, MemTxAttrs attrs)
}
GIC_DIST_CLEAR_ACTIVE(irq, cm);
}
-void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
+static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{
int cm = 1 << cpu;
int group;
DPRINTF("EOI %d\n", irq);
@@ -1486,16 +1473,10 @@ static const MemoryRegionOps gic_cpu_ops = {
.read_with_attrs = gic_do_cpu_read,
.write_with_attrs = gic_do_cpu_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-/* This function is used by nvic model */
-void gic_init_irqs_and_distributor(GICState *s)
-{
- gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
-}
-
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
int i;
GICState *s = ARM_GIC(dev);
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 6f8d242904..a2075a94db 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -73,15 +73,11 @@
#define GICC_CTLR_V2_S_MASK 0x61f
/* The special cases for the revision property: */
#define REV_11MPCORE 0
-void gic_set_pending_private(GICState *s, int cpu, int irq);
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
-void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
-void gic_update(GICState *s);
-void gic_init_irqs_and_distributor(GICState *s);
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs);
static inline bool gic_test_pending(GICState *s, int irq, int cm)
{
--
2.18.0
- [Qemu-devel] [PATCH v5 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY, (continued)
- [Qemu-devel] [PATCH v5 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 17/20] intc/arm_gic: Implement maintenance interrupt generation, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 16/20] intc/arm_gic: Implement gic_update_virt() function, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 20/20] arm/virt: Add support for GICv2 virtualization extensions, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write), Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 18/20] intc/arm_gic: Improve traces, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 06/20] intc/arm_gic: Add virtual interface register definitions, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 03/20] intc/arm_gic: Remove some dead code and put some functions static,
Luc Michel <=
- [Qemu-devel] [PATCH v5 15/20] intc/arm_gic: Implement the virtual interface registers, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq), Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio), Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 14/20] intc/arm_gic: Wire the vCPU interface, Luc Michel, 2018/07/27
- [Qemu-devel] [PATCH v5 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq, Luc Michel, 2018/07/27