Re: [Qemu-devel] [PATCH v3 18/40] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions

[Peter Maydell]

On 20 July 2018 at 05:59, Richard Henderson
<address@hidden> wrote:
> On 07/19/2018 05:54 AM, Stefan Markovic wrote:
>> +                /* SYNCI */
>> +                /* Break the TB to be able to sync copied instructions
>> +                   immediately */
>> +                ctx->base.is_jmp = DISAS_STOP;
>
> I'll note for future cleanup that while this matches all of the other 
> instances
> of SYNCI in target/mips/, this is not actually required.
>
> QEMU supports self-modifying code without any barriers or breaks whatsoever.
> (Becuase, of course, i386 as a guest requires this.)

This is true, but only if the target/ code defines
TARGET_HAS_PRECISE_SMC (which at the moment only target/i386
does), which enables some complicated code that spots
when the current TB is being modified. Most of our
other targets only support self-modifying code which
has some kind of barrier insn, and break the TB at
the barrier. (Compare Arm's handling of "isb", though
there there is also an architectural requirement to take
any pending interrupts at the barrier; I don't know if
MIPS has any similar interrupt related semantics for
their SYNCI.)

thanks
-- PMM