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[Qemu-devel] [PATCH v4 24/55] target/mips: Add handling of branch delay
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v4 24/55] target/mips: Add handling of branch delay slots for nanoMIPS |
Date: |
Tue, 24 Jul 2018 19:31:36 +0200 |
From: Matthew Fortune <address@hidden>
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a8fbbe6..1c86145 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1458,6 +1458,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+ bool has_isa_mode;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -4538,7 +4539,7 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
if (blink > 0) {
int post_delay = insn_bytes + delayslot_size;
- int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
+ int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
tcg_gen_movi_tl(cpu_gpr[blink],
ctx->base.pc_next + post_delay + lowbit);
@@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int
insn_bytes)
break;
case MIPS_HFLAG_BR:
/* unconditional branch to register */
- if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
+ if (ctx->has_isa_mode &&
+ (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {
TCGv t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -11027,7 +11029,7 @@ static void gen_compute_compact_branch(DisasContext
*ctx, uint32_t opc,
int bcond_compute = 0;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
+ int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) !=
0);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
@@ -24751,6 +24753,7 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
--
2.7.4
- [Qemu-devel] [PATCH v4 15/55] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx), (continued)
- [Qemu-devel] [PATCH v4 15/55] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx), Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 16/55] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 17/55] target/mips: Implement emulation of nanoMIPS EXTW instruction, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 18/55] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 19/55] target/mips: Add emulation of nanoMIPS branch instructions, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 20/55] target/mips: Implement MT ASE support for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 21/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 22/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 23/55] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 24/55] target/mips: Add handling of branch delay slots for nanoMIPS,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v4 25/55] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 26/55] target/mips: Add updating BadInstr, BadInstrP, BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 27/55] target/mips: Implement CP0 Config0.WR bit functionality, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 28/55] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 29/55] target/mips: Adjust exception_resume_pc() for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 30/55] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 31/55] target/mips: Adjust set_pc() for nanoMIPS, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 32/55] target/mips: Fix ERET/ERETNC behavior related to ADEL exception, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 33/55] elf: Add nanoMIPS specific variations in ELF header fields, Aleksandar Markovic, 2018/07/24
- [Qemu-devel] [PATCH v4 34/55] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/07/24