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Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consi
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH] accel/tcg: Check whether TLB entry is RAM consistently with how we set it up |
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Date: |
Tue, 24 Jul 2018 06:29:36 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 07/24/2018 05:26 AM, Peter Maydell wrote:
> On 15 July 2018 at 01:37, Richard Henderson <address@hidden> wrote:
>> On 07/13/2018 10:09 AM, Peter Maydell wrote:
>>> @@ -939,29 +935,21 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env,
>>> target_ulong addr)
>>> }
>>> assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>>> }
>>> + assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
>>
>> Don't duplicate the assert; just move it. Otherwise,
>>
>> Reviewed-by: Richard Henderson <address@hidden>
>
> I propose to put this patch into my target-arm.for-3.1 branch
> (with the duplicated assert deleted), unless you have another
> preference.
That's fine by me.
r~