Re: [Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only

[Richard Henderson]

On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> From: Stefan Markovic <address@hidden>
> 
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
>  target/mips/helper.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index 5299f21..9535131 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState 
> *env)
>                  instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
>              }
>              env->CP0_BadInstr = instr;
> +
> +            if ((env->insn_flags & ISA_NANOMIPS32) &&
> +                ((instr & 0xFC000000) == 0x60000000)) {
> +                instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
> +                env->CP0_BadInstrX = instr;
> +            }

The nanomips condition has been checked just above.
This patch should probably be merged with 24/40.


r~