Re: [Qemu-devel] [PATCH v3 22/40] target/mips: Add handling of branch delay slots for nanoMIPS

[Richard Henderson]

On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> @@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int 
> insn_bytes)
>              break;
>          case MIPS_HFLAG_BR:
>              /* unconditional branch to register */
> -            if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
> +            if (ctx->has_isa_mode &&
> +                    (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {

Is this second condition really ever true for ISA_NANOMIPS?

> @@ -24747,6 +24749,7 @@ static void 
> mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>      ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
>      ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
>      ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
> +    ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;

< 3?

Or perhaps merge the combined test here,

  ctx->has_isa_mode = (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))
                   && ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) < 3);

and only use ctx->has_isa_mode in the other locations.



r~