[Qemu-devel] [PATCH 0/4] target/arm: Implement tailchaining for M profile cores

[Peter Maydell]

Tailchaining is an optimization in handling of exception return
for M-profile cores: if we are about to pop the exception stack
for an exception return, but there is a pending exception which
is higher priority than the priority we are returning to, then
instead of unstacking and then immediately taking the exception
and stacking registers again, we can chain to the pending
exception without unstacking and stacking.

For v6M and v7M it is IMPDEF whether tailchaining happens for pending
exceptions; for v8M this is architecturally required.  Implement it
in QEMU for all M-profile cores, since in practice v6M and v7M
hardware implementations generally do have it.

(We were already doing tailchaining for derived exceptions which
happened during exception return, like the validity checks and
stack access failures; these have always been required to be
tailchained for all versions of the architecture.)

The first few patches here do some minor cleanup and bug fixing
that I noticed while working on this; patch 4 is the actual
implementation, which turns out to be pretty trivial.

thanks
-- PMM

Peter Maydell (4):
  target/arm: Improve exception-taken logging
  target/arm: Initialize exc_secure correctly in do_v7m_exception_exit()
  target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining
  target/arm: Implement tailchaining for M profile cores

 target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++-----------
 1 file changed, 36 insertions(+), 11 deletions(-)

-- 
2.17.1