Re: [Qemu-devel] [PATCH v3 11/40] target/mips: Add emulation of nanoMIPS 48-bit instructions

[Richard Henderson]

On 07/19/2018 05:54 AM, Stefan Markovic wrote:
>      case NM_P48I:
> +        insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
> +        switch ((ctx->opcode >> 16) & 0x1f) {
> +        case NM_LI48:
> +            if (rt != 0) {
> +                tcg_gen_movi_tl(cpu_gpr[rt],
> +                                extract32(ctx->opcode, 0, 16) | insn << 16);

It's probably worthwhile to hoist the offset computation above the switch; it
is used identically in every case.

> +        case NM_ADDIUGP48:
> +            if (rt != 0) {
> +                tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28],
> +                                extract32(ctx->opcode, 0, 16) | insn << 16);
> +                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);

This should use gen_op_addr_add (behaves_like('DADDIU[GP48]')).

> +        case NM_ADDIUPC48:
> +            if (rt != 0) {
> +                int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
> +                target_long addr = addr_add(ctx, ctx->base.pc_next + 6, 
> offset);
> +
> +                tcg_gen_movi_tl(cpu_gpr[rt], addr);
> +                tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);

No sign-extend needed; already done in addr_add.


r~