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[Qemu-devel] [PATCH v3 40/40] target/mips: Add definition of nanoMIPS I7
From: |
Stefan Markovic |
Subject: |
[Qemu-devel] [PATCH v3 40/40] target/mips: Add definition of nanoMIPS I7200 CPU |
Date: |
Thu, 19 Jul 2018 14:55:12 +0200 |
From: Stefan Markovic <address@hidden>
Add definition of the first nanoMIPS processor in QEMU.
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
---
target/mips/translate_init.inc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index c7ba6ee..d3f32e8 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -449,6 +449,46 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ .name = "I7200",
+ .CP0_PRid = 0x00010000,
+ .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
+ (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
+ (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
+ (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
+ (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
+ (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
+ (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
+ (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
+ (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
+ .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
+ (2 << CP0C4_IE) | (1U << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
+ (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3158FF1F,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = 0,
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_NANOMIPS32 | ASE_MICROMIPS | ASE_DSP | ASE_DSPR2 |
+ ASE_MT,
+ .mmu_type = MMU_TYPE_R4000,
+ },
#if defined(TARGET_MIPS64)
{
.name = "R4000",
--
2.7.4
- Re: [Qemu-devel] [PATCH v3 21/40] target/mips: Implement DSP ASE support for nanoMIPS, (continued)
- [Qemu-devel] [PATCH v3 28/40] target/mips: Adjust exception_resume_pc() for nanoMIPS, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 18/40] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 20/40] target/mips: Implement MT ASE support for nanoMIPS, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 36/40] mips_malta: Setup GT64120 BARs in nanoMIPS bootloader, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 29/40] target/mips: Adjust set_hflags_for_handler() for nanoMIPS, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 40/40] target/mips: Add definition of nanoMIPS I7200 CPU,
Stefan Markovic <=
- [Qemu-devel] [PATCH v3 10/40] target/mips: Add emulation of some common nanoMIPS 32-bit instructions, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 17/40] target/mips: Implement emulation of nanoMIPS EXTW instruction, Stefan Markovic, 2018/07/19