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Re: [Qemu-devel] [PULL v3 0/7] riscv-pull queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL v3 0/7] riscv-pull queue |
Date: |
Fri, 6 Jul 2018 10:10:45 +0100 |
On 6 July 2018 at 02:24, Alistair Francis <address@hidden> wrote:
> I think the SoC device should map it's own ROM (it lines up more with
> the physical SoC).
>
> I think that is how other SoC devices do it as well. I'm not really
> sure what other address space to map it to.
I generally suggest the approach where the SoC object takes a
MemoryRegion as a link QOM property. The board code puts the
board-level devices into the system memory, and then passes
that up to the SoC. The SoC creates a container MR, puts the
thing it got passed by the board in as a background region,
and then adds its own devices/ROMs/etc to the container. It
also creates the CPU object(s). Then it passes the container
to the CPU object. This approach broadly follows what the
hardware does -- the SoC controls what goes where for the
devices it is dealing with, but doesn't need to care what is
outside it. Example in hw/arm/mps2-tz.c and probably others.
thanks
-- PMM
- [Qemu-devel] [PULL v3 0/7] riscv-pull queue, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/07/03
- [Qemu-devel] [PULL v3 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/07/03
- Re: [Qemu-devel] [PULL v3 0/7] riscv-pull queue, Peter Maydell, 2018/07/04