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[Qemu-devel] [PULL v4 6/7] hw/riscv/sifive_u: Move the uart device tree
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PULL v4 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/ |
Date: |
Thu, 5 Jul 2018 18:22:14 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
---
hw/riscv/sifive_u.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 4d3ba4e624..445fe4f7fb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -194,7 +194,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
- nodename = g_strdup_printf("/address@hidden",
+ nodename = g_strdup_printf("/soc/address@hidden",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
--
2.17.1
- [Qemu-devel] [PULL v4 0/7] riscv-pull queue, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 5/7] hw/riscv/sifive_u: Set the interrupt controller number of interrupts, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/,
Alistair Francis <=
- [Qemu-devel] [PULL v4 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object, Alistair Francis, 2018/07/05
- [Qemu-devel] [PULL v4 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/07/05
- Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue, Peter Maydell, 2018/07/06
- Re: [Qemu-devel] [PULL v4 0/7] riscv-pull queue, Andreas Schwab, 2018/07/09