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[Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr |
Date: |
Tue, 3 Jul 2018 00:10:13 +0900 |
From: Richard Henderson <address@hidden>
The previous code was confused, avoiding the flush of the old entry
if the new entry is invalid. We need to flush the old page if the
old entry is valid and the new page if the new entry is valid.
This bug was masked by over-flushing elsewhere.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/sys_helper.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 7f458b0d17..c9702cd26c 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
+ target_ulong mr;
int idx;
switch (spr) {
@@ -85,12 +86,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
- if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK);
+ mr = env->tlb.dtlb[idx].mr;
+ if (mr & 1) {
+ tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
+ }
+ if (rb & 1) {
+ tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
}
env->tlb.dtlb[idx].mr = rb;
break;
-
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
env->tlb.dtlb[idx].tr = rb;
@@ -102,14 +106,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong
spr, target_ulong rb)
case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
+
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
- if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK);
+ mr = env->tlb.itlb[idx].mr;
+ if (mr & 1) {
+ tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
+ }
+ if (rb & 1) {
+ tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
}
env->tlb.itlb[idx].mr = rb;
break;
-
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
env->tlb.itlb[idx].tr = rb;
@@ -121,6 +129,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
break;
+
case TO_SPR(5, 1): /* MACLO */
env->mac = deposit64(env->mac, 0, 32, rb);
break;
--
2.17.0
- [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, (continued)
- [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 06/25] target/openrisc: Fix singlestep_enabled, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 07/25] target/openrisc: Link more translation blocks, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 08/25] target/openrisc: Split out is_user, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 09/25] target/openrisc: Exit the TB after l.mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 10/25] target/openrisc: Form the spr index from tcg, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 12/25] target/openrisc: Remove indirect function calls for mmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 13/25] target/openrisc: Merge mmu_helper.c into mmu.c, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 14/25] target/openrisc: Reduce tlb to a single dimension, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr,
Stafford Horne <=
- [Qemu-devel] [PULL v2 16/25] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 17/25] target/openrisc: Use identical sizes for ITLB and DTLB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 20/25] target/openrisc: Reorg tlb lookup, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc, Stafford Horne, 2018/07/02