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[Qemu-devel] [PULL 24/25] target/openrisc: Fix delay slot exception flag
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 24/25] target/openrisc: Fix delay slot exception flag to match spec |
Date: |
Mon, 2 Jul 2018 22:58:05 +0900 |
The delay slot exception flag is only set on the SR register during
exception. Previously it was being set on both the ESR and SR this
caused QEMU to differ from the spec. The was apparent as the linux
kernel had a bug where it could boot on QEMU but not on real hardware.
The fixed logic now matches hardware.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/interrupt.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 138ad17f00..bbae956361 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -35,13 +35,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
int exception = cs->exception_index;
env->epcr = env->pc;
- if (env->dflag) {
- env->dflag = 0;
- env->sr |= SR_DSX;
- env->epcr -= 4;
- } else {
- env->sr &= ~SR_DSX;
- }
if (exception == EXCP_SYSCALL) {
env->epcr += 4;
}
@@ -51,7 +44,10 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->eear = env->pc;
}
+ /* During exceptions esr is populared with the pre-exception sr. */
env->esr = cpu_get_sr(env);
+ /* In parallel sr is updated to disable mmu, interrupts, timers and
+ set the delay slot exception flag. */
env->sr &= ~SR_DME;
env->sr &= ~SR_IME;
env->sr |= SR_SM;
@@ -61,6 +57,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->pmr &= ~PMR_SME;
env->lock_addr = -1;
+ /* Set/clear dsx to indicate if we are in a delay slot exception. */
+ if (env->dflag) {
+ env->dflag = 0;
+ env->sr |= SR_DSX;
+ env->epcr -= 4;
+ } else {
+ env->sr &= ~SR_DSX;
+ }
+
if (exception > 0 && exception < EXCP_NR) {
static const char * const int_name[EXCP_NR] = {
[EXCP_RESET] = "RESET",
--
2.17.0
- [Qemu-devel] [PULL 14/25] target/openrisc: Reduce tlb to a single dimension, (continued)
- [Qemu-devel] [PULL 14/25] target/openrisc: Reduce tlb to a single dimension, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 15/25] target/openrisc: Fix tlb flushing in mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 16/25] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 17/25] target/openrisc: Use identical sizes for ITLB and DTLB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 19/25] target/openrisc: Increase the TLB size, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 20/25] target/openrisc: Reorg tlb lookup, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 23/25] linux-user: Fix struct sigaltstack for openrisc, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 22/25] linux-user: Implement signals for openrisc, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 24/25] target/openrisc: Fix delay slot exception flag to match spec,
Stafford Horne <=
- [Qemu-devel] [PULL 25/25] target/openrisc: Fix writes to interrupt mask register, Stafford Horne, 2018/07/02
- Re: [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Stafford Horne, 2018/07/02
- Re: [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Alex Bennée, 2018/07/02