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Re: [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask r
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register |
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Date: |
Sun, 1 Jul 2018 07:19:52 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 07/01/2018 01:12 AM, Stafford Horne wrote:
> The interrupt controller mask register (PICMR) allows writing any value
> to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt
> writing a 1 unmasks (enables) the the interrupt.
>
> For some reason the old code was or'ing the write values to the PICMR
> meaning it was not possible to ever mask a interrupt once it was
> enabled.
>
> I have tested this by running linux 4.18 and my regular checks, I don't
> see any issues.
>
> Reported-by: Davidson Francis <address@hidden>
> Signed-off-by: Stafford Horne <address@hidden>
> ---
> target/openrisc/sys_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <address@hidden>
r~