[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PULL 0/7] riscv-pull queue
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL 0/7] riscv-pull queue |
Date: |
Fri, 29 Jun 2018 15:21:08 +0100 |
On 29 June 2018 at 15:13, Alistair Francis <address@hidden> wrote:
> Can you import it manually? The armour export is below:
Aha. I tried that, which didn't work either, which prompted
me to try --verbose, which says:
e104462:xenial:qemu-for-merges$ gpg --verbose --import /tmp/alistair.gpg
gpg: armour header: Version: GnuPG v2
gpg: can't handle public key algorithm 19
gpg: pub 0E/0xE48E3BC2C123ED93 2017-12-15 Alistair Francis
<address@hidden>
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
ID "Alistair Francis <address@hidden>"
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm on user
ID "Alistair Francis <address@hidden>"
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
gpg: key 0xE48E3BC2C123ED93: unsupported public key algorithm
gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
<address@hidden>"
gpg: key 0xE48E3BC2C123ED93: skipped user ID "Alistair Francis
<address@hidden>"
gpg: key 0xE48E3BC2C123ED93: skipped subkey
gpg: key 0xE48E3BC2C123ED93: skipped subkey
gpg: key 0xE48E3BC2C123ED93: skipped subkey
gpg: key 0xE48E3BC2C123ED93: no valid user IDs
gpg: this may be caused by a missing self-signature
gpg: Total number processed: 1
gpg: w/o user IDs: 1
So the problem is that your key is using some algorithm
that's too newfangled for my gpg to cope with...
thanks
-- PMM
- [Qemu-devel] [PULL 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, (continued)
- [Qemu-devel] [PULL 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/06/27
- [Qemu-devel] [PULL 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/06/27
- [Qemu-devel] [PULL 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/06/27
- [Qemu-devel] [PULL 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/06/27
- [Qemu-devel] [PULL 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/06/27
- [Qemu-devel] [PULL 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/06/27
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Peter Maydell, 2018/06/28
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Philippe Mathieu-Daudé, 2018/06/28
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Peter Maydell, 2018/06/29
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Alistair Francis, 2018/06/29
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Alistair Francis, 2018/06/29
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Peter Maydell, 2018/06/29
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Alistair Francis, 2018/06/29
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Philippe Mathieu-Daudé, 2018/06/29
- Re: [Qemu-devel] [PULL 0/7] riscv-pull queue, Daniel P . Berrangé, 2018/06/29