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[Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr |
Date: |
Wed, 27 Jun 2018 20:03:16 -0700 |
A store to SR changes interrupt state, which should return
to the main loop to recognize that state.
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/translate.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index db149986af..59605aacca 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -877,7 +877,22 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr
*a, uint32_t insn)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- TCGv_i32 ti = tcg_const_i32(a->k);
+ TCGv_i32 ti;
+
+ /* For SR, we will need to exit the TB to recognize the new
+ * exception state. For NPC, in theory this counts as a branch
+ * (although the SPR only exists for use by an ICE). Save all
+ * of the cpu state first, allowing it to be overwritten.
+ */
+ if (dc->delayed_branch) {
+ tcg_gen_mov_tl(cpu_pc, jmp_pc);
+ tcg_gen_discard_tl(jmp_pc);
+ } else {
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
+ }
+ dc->base.is_jmp = DISAS_EXIT;
+
+ ti = tcg_const_i32(a->k);
gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
tcg_temp_free_i32(ti);
}
--
2.17.1
- [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts, (continued)
- [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 02/23] target/openrisc: Add print_insn_or1k, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 12/23] target/openrisc: Remove indirect function calls for mmu, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 14/23] target/openrisc: Reduce tlb to a single dimension, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 16/23] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 13/23] target/openrisc: Merge mmu_helper.c into mmu.c, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 15/23] target/openrisc: Fix tlb flushing in mtspr, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 19/23] target/openrisc: Increase the TLB size, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 17/23] target/openrisc: Use identical sizes for ITLB and DTLB, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 18/23] target/openrisc: Stub out handle_mmu_fault for softmmu, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 20/23] target/openrisc: Reorg tlb lookup, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 21/23] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 23/23] linux-user: Fix struct sigaltstack for openrisc, Richard Henderson, 2018/06/27