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[Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled |
Date: |
Wed, 27 Jun 2018 20:03:13 -0700 |
We failed to store to cpu_pc before raising the exception,
which caused us to re-execute the same insn that we stepped.
Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/translate.c | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 43bdf378eb..22848b17ad 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1335,31 +1335,30 @@ static void openrisc_tr_tb_stop(DisasContextBase
*dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ /* If we have already exited the TB, nothing following has effect. */
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
}
tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
- if (dc->base.is_jmp == DISAS_NEXT) {
- dc->base.is_jmp = DISAS_UPDATE;
- tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
- }
- if (unlikely(dc->base.singlestep_enabled)) {
- gen_exception(dc, EXCP_DEBUG);
- } else {
- switch (dc->base.is_jmp) {
- case DISAS_TOO_MANY:
- gen_goto_tb(dc, 0, dc->base.pc_next);
- break;
- case DISAS_NORETURN:
- break;
- case DISAS_UPDATE:
- case DISAS_EXIT:
+ switch (dc->base.is_jmp) {
+ case DISAS_TOO_MANY:
+ gen_goto_tb(dc, 0, dc->base.pc_next);
+ break;
+ case DISAS_UPDATE:
+ case DISAS_EXIT:
+ if (unlikely(dc->base.singlestep_enabled)) {
+ gen_exception(dc, EXCP_DEBUG);
+ } else {
tcg_gen_exit_tb(NULL, 0);
- break;
- default:
- g_assert_not_reached();
}
+ break;
+ default:
+ g_assert_not_reached();
}
}
--
2.17.1
- [Qemu-devel] [PATCH v3 00/23] target/openrisc improvements, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 01/23] target/openrisc: Fix mtspr shadow gprs, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 02/23] target/openrisc: Add print_insn_or1k, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 12/23] target/openrisc: Remove indirect function calls for mmu, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 14/23] target/openrisc: Reduce tlb to a single dimension, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 16/23] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 13/23] target/openrisc: Merge mmu_helper.c into mmu.c, Richard Henderson, 2018/06/27