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Re: [Qemu-devel] MSRC001_102C on EPYC (was Re: [PATCH v3] target-i386/cp
From: |
Paolo Bonzini |
Subject: |
Re: [Qemu-devel] MSRC001_102C on EPYC (was Re: [PATCH v3] target-i386/cpu: Add new EPYC CPU model) |
Date: |
Wed, 27 Jun 2018 17:07:30 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 27/06/2018 16:48, Eduardo Habkost wrote:
> Hi,
>
> On Tue, Aug 15, 2017 at 12:00:51PM -0500, Brijesh Singh wrote:
>> Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
>> family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
>>
>> The following features bits have been added/removed compare to Opteron_G5
>>
>> Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
>> fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
>> xsaveopt, xsavec, xgetbv1, arat
>>
>> Removed: xop, fma4, tbm
>>
> [...]
>> + {
>> + .name = "EPYC",
>> + .level = 0xd,
>> + .vendor = CPUID_VENDOR_AMD,
>> + .family = 23,
>> + .model = 1,
>> + .stepping = 2,
>
> These f/m/s values trigger model-specific code in Windows 10
> guests[1], and I couldn't find any public information that allow
> us to fix the problem.
At least family 17h should be set for EPYC processors.
> Windows 10 tries to set bit 15 of MSRC001_102C, in code that
> looks like workarounds for CPU Erratas.
>
> I found a Revision Guide for family 17h[2], but it has no mention
> of MSRC001_102C at all.
I also found a "Processor Programming Reference"
(https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf)
but it's not there either.
It's okay I think if KVM is modified to either return zero and ignore
writes, or return 0x8000, but I'd like confirmation from AMD too.
Paolo