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Re: [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair |
Date: |
Sun, 24 Jun 2018 17:27:22 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 |
On 06/20/2018 05:06 AM, Yongbok Kim wrote:
> +void helper_llwp(CPUMIPSState *env, target_ulong addr, uint32_t reg1,
> + uint32_t reg2, uint32_t mem_idx)
> +{
> + if (addr & 0x7) {
> + env->CP0_BadVAddr = addr;
> + do_raise_exception(env, EXCP_AdEL, GETPC());
> + }
> + env->lladdr = do_translate_address(env, addr, 0, GETPC());
> + env->active_tc.gpr[reg1] = env->llval = do_lw(env, addr, mem_idx,
> GETPC());
> + env->active_tc.gpr[reg2] = env->llval_wp = do_lw(env, addr + 4, mem_idx,
> + GETPC());
> +}
Performing two loads is a mistake. You need to perform one single 64-bit load
in order for this to be atomic. There is also no point in performing such out
of line.
> +target_ulong helper_scwp(CPUMIPSState *env, target_ulong addr,
> + uint64_t data, int mem_idx)
> +{
> + uint32_t tmp;
> + uint32_t tmp2;
> +
> + if (addr & 0x7) {
> + env->CP0_BadVAddr = addr;
> + do_raise_exception(env, EXCP_AdES, GETPC());
> + }
> + if (do_translate_address(env, addr, 1, GETPC()) == env->lladdr) {
> + tmp = do_lw(env, addr, mem_idx, GETPC());
> + tmp2 = do_lw(env, addr + 4, mem_idx, GETPC());
> + if (tmp == env->llval && tmp2 == env->llval_wp) {
> + do_sw(env, addr, (uint32_t) data, mem_idx, GETPC());
> + do_sw(env, addr + 4, (uint32_t) *(&data + 4), mem_idx, GETPC());
This must use a 64-bit atomic_cmpxchg.
This can also be done inline with
tcg_gen_atomic_cmpxchg_i64.
r~
- Re: [Qemu-devel] [PATCH 13/35] target/mips: Update gen_flt_ldst(), (continued)
- [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 15/35] target/mips: Implement nanoMIPS EXTW instruction, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 16/35] target/mips: Add has_isa_mode, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 17/35] target/mips: Add nanoMIPS load store instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 18/35] target/mips: Add nanoMIPS branch instructions, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair, Yongbok Kim, 2018/06/20
- Re: [Qemu-devel] [PATCH 19/35] target/mips: Implement nanoMIPS LLWP/SCWP pair,
Richard Henderson <=
- [Qemu-devel] [PATCH 20/35] target/mips: Fix not to update BadVAddr in Debug Mode, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 21/35] target/mips: Add nanoMIPS rotx instruction, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 22/35] target/mips: Fix data type for offset, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 23/35] target/mips: Update BadInstr{P} regs on nanoMIPS, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 24/35] target/mips: Add nanoMIPS CP0_BadInstrX register, Yongbok Kim, 2018/06/20
- [Qemu-devel] [PATCH 25/35] target/mips: Config3.ISAOnExc is read only in nanoMIPS, Yongbok Kim, 2018/06/20